{"id":"https://openalex.org/W3126267573","doi":"https://doi.org/10.1109/tcad.2021.3056337","title":"High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators","display_name":"High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators","publication_year":2021,"publication_date":"2021-02-03","ids":{"openalex":"https://openalex.org/W3126267573","doi":"https://doi.org/10.1109/tcad.2021.3056337","mag":"3126267573"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2021.3056337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3056337","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://tud.qucosa.de/id/qucosa%3A83401","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028792027","display_name":"Salim Ullah","orcid":"https://orcid.org/0000-0002-9774-9522"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Salim Ullah","raw_affiliation_strings":["Chair for Processor Design, Technische Universit&#x00E4;t Dresden, Dresden, Germany","t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, Technische Universit&#x00E4;t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058712739","display_name":"Semeen Rehman","orcid":"https://orcid.org/0000-0002-8972-0949"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Semeen Rehman","raw_affiliation_strings":["Institute of Computer Technology, Technische Universit&#x00E4;t Wien, Vienna, Austria","t Wien, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Technology, Technische Universit&#x00E4;t Wien, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"t Wien, Vienna, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005190949","display_name":"Muhammad Shafique","orcid":"https://orcid.org/0000-0002-2607-8135"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Muhammad Shafique","raw_affiliation_strings":["Division of Engineering, New York University Abu Dhabi, Abu Dhabi, UAE"],"affiliations":[{"raw_affiliation_string":"Division of Engineering, New York University Abu Dhabi, Abu Dhabi, UAE","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["Chair for Processor Design, Technische Universit&#x00E4;t Dresden, Dresden, Germany","t Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, Technische Universit&#x00E4;t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5028792027"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":8.0227,"has_fulltext":false,"cited_by_count":125,"citation_normalized_percentile":{"value":0.98169611,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":"41","issue":"2","first_page":"211","last_page":"224"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.799727201461792},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7724609375},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7527799010276794},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6811686158180237},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5314397215843201},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.49595627188682556},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4656470715999603},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4477972686290741},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4475288987159729},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34811538457870483},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3428632616996765},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.3150525689125061},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14579111337661743},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0686122477054596}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.799727201461792},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7724609375},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7527799010276794},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6811686158180237},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5314397215843201},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.49595627188682556},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4656470715999603},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4477972686290741},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4475288987159729},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34811538457870483},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3428632616996765},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.3150525689125061},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14579111337661743},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0686122477054596},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2021.3056337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2021.3056337","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:qucosa:de:qucosa:83401","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A83401","pdf_url":null,"source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"}],"best_oa_location":{"id":"pmh:oai:qucosa:de:qucosa:83401","is_oa":true,"landing_page_url":"https://tud.qucosa.de/id/qucosa%3A83401","pdf_url":null,"source":{"id":"https://openalex.org/S4377196312","display_name":"Qucosa (Saxon State and University Library Dresden)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I3132420320","host_organization_name":"SLUB Dresden","host_organization_lineage":["https://openalex.org/I3132420320"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"doc-type:Text"},"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.5899999737739563,"id":"https://metadata.un.org/sdg/8"}],"awards":[{"id":"https://openalex.org/G7276696126","display_name":null,"funder_award_id":"380524764","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1564638059","https://openalex.org/W1584008964","https://openalex.org/W1605020135","https://openalex.org/W1743414813","https://openalex.org/W1977850862","https://openalex.org/W1983849809","https://openalex.org/W2005865544","https://openalex.org/W2018758602","https://openalex.org/W2026005150","https://openalex.org/W2026445983","https://openalex.org/W2034349555","https://openalex.org/W2035378788","https://openalex.org/W2045294186","https://openalex.org/W2048773562","https://openalex.org/W2063448486","https://openalex.org/W2076793873","https://openalex.org/W2106484393","https://openalex.org/W2121819644","https://openalex.org/W2141869599","https://openalex.org/W2151097162","https://openalex.org/W2265166184","https://openalex.org/W2399535694","https://openalex.org/W2521740029","https://openalex.org/W2535375934","https://openalex.org/W2548638895","https://openalex.org/W2562079981","https://openalex.org/W2612139336","https://openalex.org/W2751750437","https://openalex.org/W3018565930","https://openalex.org/W3024342822","https://openalex.org/W3141620748","https://openalex.org/W3144137741","https://openalex.org/W4230979891","https://openalex.org/W4239085833","https://openalex.org/W4249697915","https://openalex.org/W4255177036"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W4312888585","https://openalex.org/W3212668432","https://openalex.org/W2533938775"],"abstract_inverted_index":{"Multiplication":[0],"is":[1,231],"one":[2],"of":[3,12,29,115,136,165,176,226],"the":[4,27,111,127,181,196,204,258],"widely":[5],"used":[6,210],"arithmetic":[7],"operations":[8],"in":[9,26,38,73,158,180,190,208,211,244],"a":[10,174,253],"variety":[11],"applications,":[13,215],"such":[14],"as":[15],"image/video":[16],"processing":[17],"and":[18,40,53,93,104,122,133,147,155,213,216,221,228,233,242,250],"machine":[19],"learning.":[20],"FPGA":[21,62,259],"vendors":[22,63],"provide":[23,65,91],"high-performance":[24,92],"multipliers":[25,33,230],"form":[28],"DSP":[30],"blocks.":[31],"These":[32],"are":[34],"not":[35],"only":[36],"limited":[37],"number":[39],"have":[41,202],"fixed":[42],"locations":[43],"on":[44],"FPGAs":[45,85],"but":[46],"can":[47,183],"also":[48],"create":[49],"additional":[50],"routing":[51],"delays":[52],"may":[54],"prove":[55],"inefficient":[56],"for":[57,70,84,162,219,257],"smaller":[58],"bit-width":[59],"multiplications.":[60],"Therefore,":[61],"additionally":[64],"optimized":[66],"soft":[67,80],"IP":[68,82],"cores":[69,83],"multiplication.":[71],"However,":[72],"this":[74,245],"work,":[75],"we":[76,98,201],"advocate":[77],"that":[78],"these":[79],"multiplier":[81,107,141,172,206],"still":[86],"need":[87],"better":[88],"designs":[89],"to":[90,125,139,153,178,238],"resource":[94,134],"efficiency.":[95],"Toward":[96],"this,":[97],"present":[99],"generic":[100],"area-optimized,":[101],"low-latency":[102],"accurate,":[103],"approximate":[105,171,229],"softcore":[106],"architectures,":[108,173],"which":[109],"exploit":[110],"underlying":[112],"architectural":[113],"features":[114],"FPGAs,":[116],"i.e.,":[117],"lookup":[118],"table":[119],"(LUT)":[120],"structures":[121],"fast-carry":[123],"chains":[124],"reduce":[126],"overall":[128],"critical":[129],"path":[130],"delay":[131],"(CPD)":[132],"utilization":[135],"multipliers.":[137,166],"Compared":[138],"Xilinx":[140],"LogiCORE":[142,197],"IP,":[143],"our":[144,169],"proposed":[145,205],"unsigned":[146,170],"signed":[148],"accurate":[149,227],"architecture":[150,207],"provides":[151],"up":[152,177],"25&#x0025;":[154],"53&#x0025;":[156],"reduction":[157,175],"LUT":[159],"utilization,":[160],"respectively,":[161],"different":[163],"sizes":[164],"Moreover,":[167],"with":[168,186,195],"51&#x0025;":[179],"CPD":[182],"be":[184],"achieved":[185],"an":[187],"insignificant":[188],"loss":[189],"output":[191],"accuracy":[192],"when":[193],"compared":[194],"IP.":[198],"For":[199],"illustration,":[200],"deployed":[203],"accelerators":[209],"image":[212],"video":[214],"evaluated":[217],"them":[218],"area":[220],"performance":[222],"gains.":[223],"Our":[224],"library":[225],"opensource":[232],"available":[234],"online":[235],"at":[236],"<uri>https://cfaed.tu-dresden.de/pd-downloads</uri>":[237],"fuel":[239],"further":[240],"research":[241,255],"development":[243],"area,":[246],"facilitate":[247],"reproducible":[248],"research,":[249],"thereby":[251],"enabling":[252],"new":[254],"direction":[256],"community.":[260]},"counts_by_year":[{"year":2026,"cited_by_count":10},{"year":2025,"cited_by_count":36},{"year":2024,"cited_by_count":30},{"year":2023,"cited_by_count":28},{"year":2022,"cited_by_count":19},{"year":2021,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
