{"id":"https://openalex.org/W3100453629","doi":"https://doi.org/10.1109/tcad.2020.3037885","title":"SP&amp;R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes","display_name":"SP&amp;R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes","publication_year":2020,"publication_date":"2020-11-13","ids":{"openalex":"https://openalex.org/W3100453629","doi":"https://doi.org/10.1109/tcad.2020.3037885","mag":"3100453629"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.3037885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3037885","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020579449","display_name":"Daeyeal Lee","orcid":"https://orcid.org/0000-0003-0778-0110"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daeyeal Lee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-0778-0110","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102835485","display_name":"Dongwon Park","orcid":"https://orcid.org/0000-0001-6060-9705"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dongwon Park","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-1508-3315","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053201835","display_name":"Chia-Tung Ho","orcid":"https://orcid.org/0000-0002-6479-7552"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chia-Tung Ho","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-6479-7552","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008689590","display_name":"Ilgweon Kang","orcid":"https://orcid.org/0000-0003-3842-5613"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ilgweon Kang","raw_affiliation_strings":["Digital and Signoff Group, Cadence Design Systems Inc., San Jose, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-3842-5613","affiliations":[{"raw_affiliation_string":"Digital and Signoff Group, Cadence Design Systems Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100635333","display_name":"Hayoung Kim","orcid":"https://orcid.org/0000-0001-7489-8835"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hayoung Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-7489-8835","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081085178","display_name":"Sicun Gao","orcid":"https://orcid.org/0000-0003-2524-4960"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sicun Gao","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061781904","display_name":"Bill Lin","orcid":"https://orcid.org/0000-0003-0965-7247"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bill Lin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-0965-7247","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039615312","display_name":"Chung\u2010Kuan Cheng","orcid":"https://orcid.org/0000-0002-9865-8390"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chung-Kuan Cheng","raw_affiliation_strings":["Department of Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-9865-8390","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of California at San Diego, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9085,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.74608766,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":100},"biblio":{"volume":"40","issue":"10","first_page":"2142","last_page":"2155"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.785538911819458},{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.7630757093429565},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7556626796722412},{"id":"https://openalex.org/keywords/modulo","display_name":"Modulo","score":0.675237774848938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6087307929992676},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.48601704835891724},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.47620996832847595},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4514462351799011},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.44452616572380066},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4053266644477844},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3915972411632538},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36175066232681274},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2363620102405548},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22798892855644226},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.2208627462387085}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.785538911819458},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.7630757093429565},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7556626796722412},{"id":"https://openalex.org/C54732982","wikidata":"https://www.wikidata.org/wiki/Q1415345","display_name":"Modulo","level":2,"score":0.675237774848938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6087307929992676},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.48601704835891724},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.47620996832847595},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4514462351799011},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.44452616572380066},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4053266644477844},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3915972411632538},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36175066232681274},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2363620102405548},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22798892855644226},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.2208627462387085},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2020.3037885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3037885","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5899999737739563,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G1900358287","display_name":null,"funder_award_id":"CCF-1564302","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W156574570","https://openalex.org/W602497127","https://openalex.org/W1022177737","https://openalex.org/W1480909796","https://openalex.org/W1481397690","https://openalex.org/W1496149158","https://openalex.org/W1978679823","https://openalex.org/W1986580566","https://openalex.org/W2009815534","https://openalex.org/W2040894443","https://openalex.org/W2054095206","https://openalex.org/W2061080621","https://openalex.org/W2063553865","https://openalex.org/W2093980321","https://openalex.org/W2137174619","https://openalex.org/W2138876803","https://openalex.org/W2142968870","https://openalex.org/W2144260866","https://openalex.org/W2155062262","https://openalex.org/W2174422527","https://openalex.org/W2406038381","https://openalex.org/W2525604265","https://openalex.org/W2533711050","https://openalex.org/W2588781650","https://openalex.org/W2625052843","https://openalex.org/W2626325543","https://openalex.org/W2772189580","https://openalex.org/W2773750423","https://openalex.org/W2808428854","https://openalex.org/W2810945905","https://openalex.org/W2886805397","https://openalex.org/W2921386757","https://openalex.org/W2936007546","https://openalex.org/W2937730914","https://openalex.org/W2944442872","https://openalex.org/W2946290290","https://openalex.org/W2946715554","https://openalex.org/W2952078569","https://openalex.org/W2997716136","https://openalex.org/W3007821977","https://openalex.org/W3013288889","https://openalex.org/W3090875125","https://openalex.org/W3139835941","https://openalex.org/W4245622810","https://openalex.org/W6680636136","https://openalex.org/W6752980285"],"related_works":["https://openalex.org/W2578463151","https://openalex.org/W2810367355","https://openalex.org/W2275420537","https://openalex.org/W1483783534","https://openalex.org/W4379142300","https://openalex.org/W4302330337","https://openalex.org/W2048447692","https://openalex.org/W2131919998","https://openalex.org/W4386723279","https://openalex.org/W583460537"],"abstract_inverted_index":{"In":[0],"this":[1],"article,":[2],"we":[3,53],"propose":[4],"an":[5],"automated":[6],"standard":[7,120],"cell":[8,44,92,121,131],"synthesis":[9],"framework,":[10,52],"SP&R,":[11],"which":[12],"simultaneously":[13],"solves":[14],"P&R":[15],"without":[16],"deploying":[17],"any":[18],"sequential/separate":[19],"operations,":[20],"by":[21,106,137],"a":[22,87,117],"novel":[23],"dynamic":[24],"pin":[25],"allocation":[26],"scheme.":[27],"The":[28],"proposed":[29],"SP&R":[30,73,89],"utilizes":[31],"the":[32,51,70,83,114,125],"multiobjective":[33],"optimization":[34],"feature":[35],"of":[36,50,116],"satisfiability":[37],"modulo":[38],"theories":[39],"(SMT)":[40],"to":[41,69,76,95,124],"obtain":[42],"optimal":[43],"layouts.":[45],"To":[46],"achieve":[47],"practical":[48],"scalability":[49],"develop":[54],"various":[55],"search-space":[56],"reduction":[57],"techniques,":[58],"including":[59],"breaking":[60],"symmetry,":[61],"conditional":[62],"assignment/localization,":[63],"and":[64,100,133,142],"cell/objective":[65],"function":[66],"partitioning.":[67],"Compared":[68,123],"previous":[71],"work,":[72],"achieves":[74],"20.8\u00d7":[75],"131.7\u00d7":[77],"runtime":[78],"improvements":[79],"on":[80],"average":[81],"across":[82],"design-rule":[84],"sets.":[85],"As":[86],"result,":[88],"successfully":[90],"produces":[91],"layouts":[93],"up":[94],"36":[96],"field-effect":[97],"transistors":[98],"(FETs)":[99],"27":[101],"nets":[102],"within":[103],"1.75":[104],"h":[105],"orchestrating":[107],"all":[108],"innovative":[109],"tactics":[110],"together,":[111],"resulting":[112],"in":[113],"generation":[115],"whole":[118],"7-nm":[119],"library.":[122],"known":[126],"layouts,":[127],"our":[128],"work":[129],"improves":[130],"size":[132],"#":[134],"M2":[135],"tracks":[136],"0.1":[138],"contacted":[139],"poly":[140],"pitch":[141],"0.3":[143],"tracks,":[144],"respectively.":[145]},"counts_by_year":[{"year":2026,"cited_by_count":9},{"year":2025,"cited_by_count":18},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
