{"id":"https://openalex.org/W3089396352","doi":"https://doi.org/10.1109/tcad.2020.3028350","title":"<i>ReLAccS</i>: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems","display_name":"<i>ReLAccS</i>: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems","publication_year":2020,"publication_date":"2020-10-02","ids":{"openalex":"https://openalex.org/W3089396352","doi":"https://doi.org/10.1109/tcad.2020.3028350","mag":"3089396352"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.3028350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3028350","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002474306","display_name":"Akhil Raj Baranwal","orcid":"https://orcid.org/0000-0003-1024-9101"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Akhil Raj Baranwal","raw_affiliation_strings":["Chair for Processor Design, TU Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, TU Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028792027","display_name":"Salim Ullah","orcid":"https://orcid.org/0000-0002-9774-9522"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Salim Ullah","raw_affiliation_strings":["Chair for Processor Design, TU Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, TU Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051064456","display_name":"Siva Satyendra Sahoo","orcid":"https://orcid.org/0000-0002-2243-5350"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Siva Satyendra Sahoo","raw_affiliation_strings":["Chair for Processor Design, TU Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, TU Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100755285","display_name":"Akash Kumar","orcid":"https://orcid.org/0000-0001-7125-1737"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Akash Kumar","raw_affiliation_strings":["Chair for Processor Design, TU Dresden, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Chair for Processor Design, TU Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5002474306"],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":0.728,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.7102473,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"40","issue":"9","first_page":"1754","last_page":"1767"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reinforcement-learning","display_name":"Reinforcement learning","score":0.8607118129730225},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7722053527832031},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6965911388397217},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6448707580566406},{"id":"https://openalex.org/keywords/a-priori-and-a-posteriori","display_name":"A priori and a posteriori","score":0.48045915365219116},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4729606509208679},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4306790232658386},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4226631224155426},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3947312831878662},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3520233929157257},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.29559892416000366},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21288233995437622}],"concepts":[{"id":"https://openalex.org/C97541855","wikidata":"https://www.wikidata.org/wiki/Q830687","display_name":"Reinforcement learning","level":2,"score":0.8607118129730225},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7722053527832031},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6965911388397217},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6448707580566406},{"id":"https://openalex.org/C75553542","wikidata":"https://www.wikidata.org/wiki/Q178161","display_name":"A priori and a posteriori","level":2,"score":0.48045915365219116},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4729606509208679},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4306790232658386},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4226631224155426},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3947312831878662},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3520233929157257},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.29559892416000366},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21288233995437622},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2020.3028350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3028350","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.4300000071525574}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323803","display_name":"Bundesministerium f\u00fcr Wirtschaft und Energie","ror":"https://ror.org/02vgg2808"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W41554520","https://openalex.org/W1155403144","https://openalex.org/W1552655566","https://openalex.org/W1569205584","https://openalex.org/W1658008008","https://openalex.org/W1757796397","https://openalex.org/W2062820925","https://openalex.org/W2096875061","https://openalex.org/W2113226229","https://openalex.org/W2121863487","https://openalex.org/W2145339207","https://openalex.org/W2257979135","https://openalex.org/W2471791811","https://openalex.org/W2554043083","https://openalex.org/W2557443516","https://openalex.org/W2616729100","https://openalex.org/W2777105798","https://openalex.org/W2782804634","https://openalex.org/W2808980609","https://openalex.org/W2901621510","https://openalex.org/W2904195769","https://openalex.org/W2907816230","https://openalex.org/W2915058268","https://openalex.org/W2938157874","https://openalex.org/W2944942025","https://openalex.org/W2998165854","https://openalex.org/W4234813165","https://openalex.org/W4239085833","https://openalex.org/W4255177036","https://openalex.org/W4298857966","https://openalex.org/W6633075984","https://openalex.org/W6730325281","https://openalex.org/W6747258343","https://openalex.org/W6752737636"],"related_works":["https://openalex.org/W2798215405","https://openalex.org/W2990962948","https://openalex.org/W2111241003","https://openalex.org/W4388311650","https://openalex.org/W1974056099","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441"],"abstract_inverted_index":{"Reinforcement":[0],"learning":[1,7],"(RL),":[2],"specifically":[3],"Q-learning,":[4],"with":[5,127,146],"human-like":[6],"abilities":[8],"to":[9,85,94,102,140],"learn":[10],"from":[11],"experience":[12],"without":[13],"any":[14],"a":[15,45],"priori":[16],"data,":[17],"is":[18],"being":[19],"increasingly":[20],"used":[21,121],"in":[22,25,37,83,143,149],"embedded":[23],"systems":[24],"the":[26,34,51,72,76,80,87,104,111,133],"field":[27],"of":[28,65,110,124,151],"control":[29],"and":[30,44,79,107,130],"navigation.":[31],"However,":[32],"finding":[33],"optimal":[35],"policy":[36],"this":[38,56],"approach":[39],"can":[40,119],"be":[41,120],"highly":[42],"compute-intensive,":[43],"software-only":[46],"implementation":[47],"may":[48],"not":[49],"satisfy":[50],"application's":[52],"timing":[53],"constraints.":[54],"To":[55],"end,":[57],"we":[58,74,97,114],"propose":[59,98,115],"optimization":[60],"methods":[61],"at":[62,71],"multiple":[63],"levels":[64],"accelerator":[66],"design":[67],"for":[68,122,131],"RL.":[69],"Specifically,":[70],"architecture-level,":[73],"exploit":[75],"instruction-level":[77],"parallelism":[78,82],"spatial":[81],"FPGAs":[84],"improve":[86],"throughput":[88],"over":[89],"state-of-the-art":[90],"designs":[91],"by":[92],"up":[93,139],"34%.":[95],"Further,":[96],"lookup":[99],"table-level":[100],"optimizations":[101],"reduce":[103],"resource":[105],"utilization":[106],"power":[108,135,144],"dissipation":[109,145],"accelerator.":[112],"Finally,":[113],"algorithm-level":[116],"approximation":[117],"that":[118],"acceleration":[123],"Q-learning":[125],"problems":[126],"more":[128],"states":[129],"reducing":[132],"peak":[134],"dissipation.":[136],"We":[137],"report":[138],"10\u00d7":[141],"reduction":[142],"marginal":[147],"degradation":[148],"quality":[150],"results.":[152]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}
