{"id":"https://openalex.org/W3089695250","doi":"https://doi.org/10.1109/tcad.2020.3012748","title":"HopliteRT: Real-Time NoC for FPGA","display_name":"HopliteRT: Real-Time NoC for FPGA","publication_year":2020,"publication_date":"2020-10-02","ids":{"openalex":"https://openalex.org/W3089695250","doi":"https://doi.org/10.1109/tcad.2020.3012748","mag":"3089695250"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.3012748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3012748","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016269724","display_name":"Yilian Ribot Gonz\u00e1lez","orcid":"https://orcid.org/0000-0002-4089-7794"},"institutions":[{"id":"https://openalex.org/I83863532","display_name":"Polytechnic Institute of Porto","ror":"https://ror.org/04988re48","country_code":"PT","type":"education","lineage":["https://openalex.org/I83863532"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Yilian Ribot Gonzalez","raw_affiliation_strings":["CISTER Research Centre, ISEP, Polytechnic Institute of Porto, Porto, Portugal"],"raw_orcid":"https://orcid.org/0000-0002-4089-7794","affiliations":[{"raw_affiliation_string":"CISTER Research Centre, ISEP, Polytechnic Institute of Porto, Porto, Portugal","institution_ids":["https://openalex.org/I83863532"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023696057","display_name":"Geoffrey Nelissen","orcid":"https://orcid.org/0000-0003-4141-6718"},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Geoffrey Nelissen","raw_affiliation_strings":["Department of Mathematics and Computer Science, Eindhoven University of Technology, Eindhoven, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Mathematics and Computer Science, Eindhoven University of Technology, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5016269724"],"corresponding_institution_ids":["https://openalex.org/I83863532"],"apc_list":null,"apc_paid":null,"fwci":1.133,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.80589626,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"39","issue":"11","first_page":"3650","last_page":"3661"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8079555034637451},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7639119625091553},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7563997507095337},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.7160947322845459},{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.6623305678367615},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6035202145576477},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.587604820728302},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5338154435157776},{"id":"https://openalex.org/keywords/quality-of-service","display_name":"Quality of service","score":0.5060409903526306},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.42699673771858215},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3547596037387848},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3043358027935028}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8079555034637451},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7639119625091553},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7563997507095337},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.7160947322845459},{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.6623305678367615},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6035202145576477},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.587604820728302},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5338154435157776},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.5060409903526306},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.42699673771858215},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3547596037387848},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3043358027935028},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcad.2020.3012748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3012748","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/5335f98c-8ebb-468d-972b-b0967a125bc6","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/5335f98c-8ebb-468d-972b-b0967a125bc6","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ribot Gonz\u00e1lez, Y & Nelissen, G 2020, 'HopliteRT* : Real-Time NoC for FPGA', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 11, 9211415, pp. 3650-3661. https://doi.org/10.1109/TCAD.2020.3012748","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/5335f98c-8ebb-468d-972b-b0967a125bc6","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/5335f98c-8ebb-468d-972b-b0967a125bc6","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11):9211415, 3650 - 3661. Institute of Electrical and Electronics Engineers","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W25478891","https://openalex.org/W1574396483","https://openalex.org/W1644436786","https://openalex.org/W1732956772","https://openalex.org/W1976785975","https://openalex.org/W1976878754","https://openalex.org/W2018391508","https://openalex.org/W2020607902","https://openalex.org/W2022098216","https://openalex.org/W2089797152","https://openalex.org/W2095314640","https://openalex.org/W2101331904","https://openalex.org/W2105996829","https://openalex.org/W2116514950","https://openalex.org/W2128728233","https://openalex.org/W2136257237","https://openalex.org/W2141440050","https://openalex.org/W2159526626","https://openalex.org/W2383338720","https://openalex.org/W2528729421","https://openalex.org/W2600117321","https://openalex.org/W2602760423","https://openalex.org/W2752980382","https://openalex.org/W2769458067","https://openalex.org/W2785317661","https://openalex.org/W2794770452","https://openalex.org/W2804241905","https://openalex.org/W2809390521","https://openalex.org/W2917839487","https://openalex.org/W2944870195","https://openalex.org/W2965711623","https://openalex.org/W2975051067","https://openalex.org/W2988808365","https://openalex.org/W2990953185","https://openalex.org/W3089695250","https://openalex.org/W3140062895","https://openalex.org/W4229823398","https://openalex.org/W4248067098","https://openalex.org/W6767808086","https://openalex.org/W7066630288"],"related_works":["https://openalex.org/W1761969858","https://openalex.org/W2122279357","https://openalex.org/W1821888792","https://openalex.org/W2087566584","https://openalex.org/W4380607193","https://openalex.org/W2121539644","https://openalex.org/W2943902928","https://openalex.org/W71953811","https://openalex.org/W2132512458","https://openalex.org/W3089695250"],"abstract_inverted_index":{"With":[0],"the":[1,36,43,63,70,81,106,121,134],"increasing":[2],"number":[3],"of":[4,38,45,85,103,108,128,136,138,144],"computation":[5],"nodes":[6],"integrated":[7],"in":[8,21,59,66,80,111,162],"multi":[9],"and":[10,87,123,164],"many-core":[11],"platforms,":[12],"network-on-chips":[13],"(NoCs)":[14],"emerged":[15],"as":[16],"a":[17,26,78,90,167],"new":[18,27,91],"communication":[19],"medium":[20],"systems-on-chips":[22],"(SoCs).":[23],"HopliteRT":[24,109],"is":[25,95],"NoC":[28,158],"design":[29],"that":[30,94,105],"was":[31],"recently":[32],"proposed":[33,110,157],"to":[34,68],"address":[35],"needs":[37],"real-time":[39],"systems":[40],"whilst":[41],"respecting":[42],"constraints":[44],"field-programmable":[46],"gate":[47],"array":[48],"(FPGA)":[49],"platforms.":[50],"In":[51],"this":[52,112],"article,":[53],"we:":[54],"1)":[55],"introduce":[56],"priority-based":[57],"routing":[58],"HopliteRT;":[60,86],"2)":[61],"change":[62],"network":[64],"topology":[65],"order":[67],"improve":[69],"packets'":[71],"worst-case":[72],"traversal":[73,126],"time":[74,127],"(WCTT);":[75],"3)":[76],"identify":[77],"flaw":[79],"existing":[82],"timing":[83,92,142],"analysis":[84,93],"4)":[88],"develop":[89],"proven":[96],"correct.":[97],"We":[98],"also":[99],"show":[100],"by":[101],"means":[102],"experiments":[104],"modifications":[107],"article":[113],"allows":[114],"for":[115,151,166],"at":[116],"least":[117],"2\u00d7":[118],"improvement":[119],"on":[120],"worst":[122],"average":[124],"case":[125],"high":[129,145],"priority":[130,146],"packets,":[131],"without":[132],"impacting":[133],"quality":[135],"service":[137],"low-priority":[139],"packets.":[140],"The":[141,156],"properties":[143],"flows":[147],"are":[148],"greatly":[149],"improved":[150],"negligible":[152],"additional":[153],"hardware":[154],"costs.":[155],"has":[159],"been":[160],"implemented":[161],"Verilog":[163],"synthesized":[165],"Xilinx":[168],"Virtex-7":[169],"FPGA":[170],"platform.":[171]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2020-10-08T00:00:00"}