{"id":"https://openalex.org/W3091205277","doi":"https://doi.org/10.1109/tcad.2020.3012213","title":"Hardware Memory Management for Future Mobile Hybrid Memory Systems","display_name":"Hardware Memory Management for Future Mobile Hybrid Memory Systems","publication_year":2020,"publication_date":"2020-10-02","ids":{"openalex":"https://openalex.org/W3091205277","doi":"https://doi.org/10.1109/tcad.2020.3012213","mag":"3091205277"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.3012213","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3012213","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045341750","display_name":"Fei Wen","orcid":"https://orcid.org/0000-0002-8789-8495"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fei Wen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-8789-8495","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031409712","display_name":"Mian Qin","orcid":"https://orcid.org/0000-0003-1753-3914"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mian Qin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"],"raw_orcid":"https://orcid.org/0000-0003-1753-3914","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082578661","display_name":"Paul V. Gratz","orcid":"https://orcid.org/0000-0001-7120-7189"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul V. Gratz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"],"raw_orcid":"https://orcid.org/0000-0001-7120-7189","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101890763","display_name":"A. L. Narasimha Reddy","orcid":"https://orcid.org/0009-0008-2217-2563"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. L. Narasimha Reddy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91045830"],"apc_list":null,"apc_paid":null,"fwci":1.716,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.84781089,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"39","issue":"11","first_page":"3627","last_page":"3637"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7776509523391724},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.74497389793396},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6737419962882996},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.6078548431396484},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5843897461891174},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5618626475334167},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5423117876052856},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.53140789270401},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5285643339157104},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.49704912304878235},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4733212888240814},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.44684404134750366},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44228243827819824},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.41198551654815674},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.41173580288887024},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11169427633285522}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7776509523391724},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.74497389793396},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6737419962882996},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.6078548431396484},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5843897461891174},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5618626475334167},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5423117876052856},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.53140789270401},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5285643339157104},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.49704912304878235},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4733212888240814},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.44684404134750366},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44228243827819824},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.41198551654815674},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.41173580288887024},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11169427633285522},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2020.3012213","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3012213","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G1314565618","display_name":null,"funder_award_id":"I/UCRC-1439722","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G670996187","display_name":null,"funder_award_id":"FoMR-1823403","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1975698617","https://openalex.org/W1987201308","https://openalex.org/W1994717635","https://openalex.org/W2013626513","https://openalex.org/W2018774711","https://openalex.org/W2036403064","https://openalex.org/W2045034807","https://openalex.org/W2047043979","https://openalex.org/W2048588974","https://openalex.org/W2054308357","https://openalex.org/W2064111805","https://openalex.org/W2082982763","https://openalex.org/W2102449048","https://openalex.org/W2104305170","https://openalex.org/W2134345525","https://openalex.org/W2144570882","https://openalex.org/W2147657366","https://openalex.org/W2149055332","https://openalex.org/W2152933730","https://openalex.org/W2169865228","https://openalex.org/W2213297816","https://openalex.org/W2258963578","https://openalex.org/W2487018225","https://openalex.org/W2619024801","https://openalex.org/W2763836248","https://openalex.org/W2764085896","https://openalex.org/W2805359884","https://openalex.org/W2899311583","https://openalex.org/W6661682806","https://openalex.org/W6681515304","https://openalex.org/W6755999810"],"related_works":["https://openalex.org/W4285257158","https://openalex.org/W2898989424","https://openalex.org/W4293159259","https://openalex.org/W1494152240","https://openalex.org/W1030357071","https://openalex.org/W63036740","https://openalex.org/W4238754064","https://openalex.org/W2188534734","https://openalex.org/W1981423095","https://openalex.org/W2140144029"],"abstract_inverted_index":{"The":[0,235],"current":[1],"mobile":[2,71],"applications":[3],"have":[4],"rapidly":[5],"growing":[6],"memory":[7,14,20,27,79,146,150,167,202,213,226],"footprints,":[8],"posing":[9],"a":[10,30,48,102,153,165,173,178,191,243,251],"great":[11],"challenge":[12],"for":[13,185],"system":[15,158,218],"design.":[16],"Insufficient":[17],"DRAM":[18,50,61,68,96,129,183],"main":[19],"will":[21],"incur":[22,134],"frequent":[23],"data":[24,194,197],"swaps":[25],"between":[26],"and":[28,37,55,97,113,130,137,196],"storage,":[29],"process":[31],"that":[32,170,205,239,259],"hurts":[33],"performance,":[34],"consumes":[35],"energy,":[36],"deteriorates":[38],"the":[39,57,70,82,119,141,149,182,209,217,224,233,264],"write":[40],"endurance":[41],"of":[42,67,105,143,156,181,193,211],"typical":[43],"flash":[44],"storage":[45],"devices.":[46],"Alternately,":[47],"larger":[49],"has":[51,81,116,123],"higher":[52,91,135],"leakage":[53],"power":[54],"drains":[56],"battery":[58],"faster.":[59],"Furthermore,":[60],"scaling":[62],"trends":[63],"make":[64],"further":[65],"growth":[66],"in":[69,148,172,246,263],"space":[72],"prohibitive":[73],"due":[74,88],"to":[75,84,89,128,232],"cost.":[76],"Emerging":[77],"nonvolatile":[78],"(NVM)":[80],"potential":[83],"alleviate":[85],"these":[86,144],"issues":[87],"its":[90],"capacity":[92],"per":[93],"cost":[94],"than":[95],"minimal":[98],"static":[99],"power.":[100],"Recently,":[101],"wide":[103],"spectrum":[104],"NVM":[106,122,131],"technologies,":[107],"including":[108],"phase-change":[109],"memories":[110],"(PCMs),":[111],"memristor,":[112],"3-D":[114],"XPoint":[115],"emerged.":[117],"Despite":[118],"mentioned":[120],"advantages,":[121],"longer":[124],"access":[125],"latency":[126,227],"compared":[127],"writes":[132,231],"can":[133],"latencies":[136],"wear":[138],"costs.":[139],"Therefore,":[140],"integration":[142],"new":[145],"technologies":[147],"hierarchy":[151],"requires":[152],"fundamental":[154],"rearchitecting":[155],"traditional":[157],"designs.":[159],"In":[160],"this":[161,201,220],"work,":[162],"we":[163,206,222],"propose":[164],"hardware-accelerated":[166],"manager":[168,203],"(HMMU)":[169],"addresses":[171],"flat":[174],"address":[175],"space,":[176],"with":[177,219,249],"small":[179],"partition":[180],"reserved":[184],"subpage":[186],"block-level":[187],"management.":[188],"We":[189],"design":[190,241],"set":[192],"placement":[195],"migration":[198],"policies":[199],"within":[200],"such":[204],"may":[207],"exploit":[208],"advantages":[210],"each":[212],"technology.":[214],"By":[215],"augmenting":[216],"HMMU,":[221],"reduce":[223],"overall":[225],"while":[228],"also":[229],"reducing":[230],"NVM.":[234],"experimental":[236],"results":[237],"show":[238],"our":[240],"achieves":[242],"39%":[244],"reduction":[245],"energy":[247],"consumption":[248],"only":[250],"12%":[252],"performance":[253],"degradation":[254],"versus":[255],"an":[256],"all-DRAM":[257],"baseline":[258],"is":[260],"likely":[261],"untenable":[262],"future.":[265]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}