{"id":"https://openalex.org/W3006236305","doi":"https://doi.org/10.1109/tcad.2020.3012172","title":"AnyHLS: High-Level Synthesis With Partial Evaluation","display_name":"AnyHLS: High-Level Synthesis With Partial Evaluation","publication_year":2020,"publication_date":"2020-10-02","ids":{"openalex":"https://openalex.org/W3006236305","doi":"https://doi.org/10.1109/tcad.2020.3012172","mag":"3006236305"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.3012172","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3012172","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["arxiv","crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2002.05796","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061837918","display_name":"M. Akif \u00d6zkan","orcid":"https://orcid.org/0000-0001-5067-2268"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Akif Ozkan","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander University Erlangen-N\u00fcrnberg, Erlangen, Germany"],"raw_orcid":"https://orcid.org/0000-0001-5067-2268","affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander University Erlangen-N\u00fcrnberg, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077035896","display_name":"Ars\u00e8ne P\u00e9rard\u2010Gayot","orcid":null},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Arsene Perard-Gayot","raw_affiliation_strings":["Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024954324","display_name":"Richard Membarth","orcid":"https://orcid.org/0000-0002-9979-7579"},"institutions":[{"id":"https://openalex.org/I33256026","display_name":"German Research Centre for Artificial Intelligence","ror":"https://ror.org/01ayc5b57","country_code":"DE","type":"funder","lineage":["https://openalex.org/I33256026"]},{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Richard Membarth","raw_affiliation_strings":["Department of Agents and Simulated Reality, German Research Center for Artificial Intelligence, Kaiserslautern, Germany","Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Agents and Simulated Reality, German Research Center for Artificial Intelligence, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I33256026"]},{"raw_affiliation_string":"Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026514026","display_name":"Philipp Slusallek","orcid":null},"institutions":[{"id":"https://openalex.org/I33256026","display_name":"German Research Centre for Artificial Intelligence","ror":"https://ror.org/01ayc5b57","country_code":"DE","type":"funder","lineage":["https://openalex.org/I33256026"]},{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Philipp Slusallek","raw_affiliation_strings":["Department of Agents and Simulated Reality, German Research Center for Artificial Intelligence, Kaiserslautern, Germany","Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Agents and Simulated Reality, German Research Center for Artificial Intelligence, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I33256026"]},{"raw_affiliation_string":"Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110249437","display_name":"Roland Leisa","orcid":null},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Roland Leisa","raw_affiliation_strings":["Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018809145","display_name":"Sebastian Hack","orcid":"https://orcid.org/0000-0002-3387-2134"},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian Hack","raw_affiliation_strings":["Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Saarland University (UdS), Saarbr\u00fccken, Germany","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076672029","display_name":"J\u00fcrgen Teich","orcid":"https://orcid.org/0000-0001-6285-5862"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jurgen Teich","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander University Erlangen-N\u00fcrnberg, Erlangen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander University Erlangen-N\u00fcrnberg, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072039340","display_name":"Frank Hannig","orcid":"https://orcid.org/0000-0003-3663-6484"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Hannig","raw_affiliation_strings":["Department of Computer Science, Friedrich-Alexander University Erlangen-N\u00fcrnberg, Erlangen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Friedrich-Alexander University Erlangen-N\u00fcrnberg, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.0898,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.9457582,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"39","issue":"11","first_page":"3202","last_page":"3214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8643118143081665},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.673526406288147},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.6381821632385254},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5911198854446411},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.5439602732658386},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5217434167861938},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5163894295692444},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4892549514770508},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.48480263352394104},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4724593162536621},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.44402462244033813},{"id":"https://openalex.org/keywords/vendor","display_name":"Vendor","score":0.4410496652126312},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.43844375014305115},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.41904282569885254},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.41899916529655457},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.41628140211105347},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.2036668360233307},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.19387224316596985}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8643118143081665},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.673526406288147},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.6381821632385254},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5911198854446411},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.5439602732658386},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5217434167861938},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5163894295692444},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4892549514770508},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.48480263352394104},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4724593162536621},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.44402462244033813},{"id":"https://openalex.org/C2777338717","wikidata":"https://www.wikidata.org/wiki/Q1762621","display_name":"Vendor","level":2,"score":0.4410496652126312},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.43844375014305115},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.41904282569885254},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.41899916529655457},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.41628140211105347},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2036668360233307},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.19387224316596985},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tcad.2020.3012172","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.3012172","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:arXiv.org:2002.05796","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2002.05796","pdf_url":"https://arxiv.org/pdf/2002.05796","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"pmh:oai:ub-madoc.bib.uni-mannheim.de:60588","is_oa":false,"landing_page_url":"https://madoc.bib.uni-mannheim.de/60588/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401433","display_name":"MADOC (University of Mannheim)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177802217","host_organization_name":"University of Mannheim","host_organization_lineage":["https://openalex.org/I177802217"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Zeitschriftenartikel"},{"id":"doi:10.22028/d291-47772","is_oa":true,"landing_page_url":"https://doi.org/10.22028/d291-47772","pdf_url":null,"source":{"id":"https://openalex.org/S7407052975","display_name":"Universit\u00e4t des Saarlandes","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"Collection"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2002.05796","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2002.05796","pdf_url":"https://arxiv.org/pdf/2002.05796","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.5899999737739563,"display_name":"Decent work and economic growth"}],"awards":[{"id":"https://openalex.org/G7110753022","display_name":null,"funder_award_id":"146371743\u2014TRR 89","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":51,"referenced_works":["https://openalex.org/W1556604985","https://openalex.org/W1558703166","https://openalex.org/W1607247974","https://openalex.org/W1912157869","https://openalex.org/W1980208272","https://openalex.org/W1983394510","https://openalex.org/W1995041765","https://openalex.org/W2024381286","https://openalex.org/W2055312318","https://openalex.org/W2094998159","https://openalex.org/W2106574988","https://openalex.org/W2106962797","https://openalex.org/W2131023841","https://openalex.org/W2141280299","https://openalex.org/W2160183719","https://openalex.org/W2166029537","https://openalex.org/W2343695530","https://openalex.org/W2405102949","https://openalex.org/W2466242877","https://openalex.org/W2517689844","https://openalex.org/W2524530727","https://openalex.org/W2544002786","https://openalex.org/W2555127608","https://openalex.org/W2612093424","https://openalex.org/W2740250250","https://openalex.org/W2793009992","https://openalex.org/W2798482398","https://openalex.org/W2803374624","https://openalex.org/W2809170821","https://openalex.org/W2886649770","https://openalex.org/W2889424113","https://openalex.org/W2895073260","https://openalex.org/W2898442528","https://openalex.org/W2899691047","https://openalex.org/W2905135312","https://openalex.org/W2925360983","https://openalex.org/W2949967139","https://openalex.org/W2952724890","https://openalex.org/W2954600699","https://openalex.org/W2966394518","https://openalex.org/W2986373782","https://openalex.org/W3108085245","https://openalex.org/W3147312088","https://openalex.org/W3161860068","https://openalex.org/W4235535008","https://openalex.org/W4242052194","https://openalex.org/W4299809807","https://openalex.org/W6737776912","https://openalex.org/W6752210369","https://openalex.org/W6753932278","https://openalex.org/W6770162192"],"related_works":["https://openalex.org/W2005854230","https://openalex.org/W2366672283","https://openalex.org/W1761969858","https://openalex.org/W2168113051","https://openalex.org/W4312121077","https://openalex.org/W1748531671","https://openalex.org/W4241206086","https://openalex.org/W2109697164","https://openalex.org/W2090808187","https://openalex.org/W2055606014"],"abstract_inverted_index":{"Field":[0],"programmable":[1],"gate":[2],"arrays":[3],"(FPGAs)":[4],"excel":[5],"in":[6,96,106,126,208],"low":[7],"power":[8],"and":[9,129,154,167,187,224],"high":[10],"throughput":[11],"computations,":[12],"but":[13,48],"they":[14],"are":[15,92,228],"challenging":[16],"to":[17,31,60,103,122,135,147,165,168,204],"program.":[18],"Traditionally,":[19],"developers":[20],"rely":[21],"on":[22,162,174],"hardware":[23,34,63,70],"description":[24],"languages,":[25],"such":[26,151],"as":[27,152,158,220],"Verilog":[28],"or":[29,110],"VHDL":[30],"specify":[32],"the":[33,37,44,62,97,137,141,170,199,213],"behavior":[35],"at":[36,198],"register-transfer":[38],"level.":[39],"High-level":[40],"synthesis":[41,226],"(HLS)":[42],"raises":[43],"level":[45,139],"of":[46,65,82,140,177,215],"abstraction":[47,138],"still":[49],"requires":[50],"FPGA":[51,124],"design":[52,111],"knowledge.":[53],"Programmers":[54],"usually":[55],"write":[56],"pragma-annotated":[57],"C/C++":[58],"programs":[59],"define":[61],"architecture":[64],"an":[66,120],"application.":[67],"However,":[68],"each":[69],"vendor":[71],"extends":[72],"its":[73,78,225],"own":[74,79],"C":[75],"dialect":[76],"using":[77],"vendor-specific":[80,180,196],"set":[81],"pragmas.":[83],"This":[84,99],"prevents":[85],"portability":[86],"across":[87],"different":[88],"vendors.":[89],"Furthermore,":[90],"pragmas":[91,197],"not":[93],"first-class":[94],"citizens":[95],"language.":[98],"makes":[100],"it":[101],"hard":[102],"use":[104],"them":[105],"a":[107,127,175,210,221],"modular":[108,128],"way":[109],"proper":[112],"abstractions.":[113,178],"In":[114,202],"this":[115,238],"article,":[116],"we":[117],"present":[118],"AnyHLS,":[119],"approach":[121],"synthesize":[123],"designs":[125],"abstract":[130],"way.":[131],"AnyHLS":[132],"is":[133,183,191,218],"able":[134],"raise":[136],"existing":[142],"HLS":[143,181],"tools":[144],"by":[145,193],"resorting":[146],"programming":[148],"language":[149,234],"features":[150],"types":[153],"higher":[155],"order":[156,203],"functions":[157],"follows.":[159],"It":[160],"relies":[161],"partial":[163],"evaluation":[164],"specialize":[166],"optimize":[169],"user":[171],"application":[172],"based":[173],"library":[176,211],"Then,":[179],"code":[182],"generated":[184],"for":[185,212,237],"Intel":[186],"Xilinx":[188],"FPGAs.":[189],"Portability":[190],"obtained":[192],"avoiding":[194],"any":[195],"source":[200],"code.":[201],"validate":[205],"achievable":[206],"gains":[207],"productivity,":[209],"domain":[214],"image":[216],"processing":[217],"introduced":[219],"case":[222],"study,":[223],"results":[227],"compared":[229],"with":[230],"several":[231],"state-of-the-art":[232],"domain-specific":[233],"(DSL)":[235],"approaches":[236],"domain.":[239]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2}],"updated_date":"2026-07-03T08:13:44.112507","created_date":"2025-10-10T00:00:00"}