{"id":"https://openalex.org/W3021482280","doi":"https://doi.org/10.1109/tcad.2020.2990832","title":"Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism","display_name":"Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism","publication_year":2020,"publication_date":"2020-04-28","ids":{"openalex":"https://openalex.org/W3021482280","doi":"https://doi.org/10.1109/tcad.2020.2990832","mag":"3021482280"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.2990832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.2990832","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025152730","display_name":"Zhanwei Zhong","orcid":"https://orcid.org/0000-0002-0946-574X"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zhanwei Zhong","raw_affiliation_strings":["Duke University, Durham, NC, USA"],"raw_orcid":"https://orcid.org/0000-0002-0946-574X","affiliations":[{"raw_affiliation_string":"Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100451571","display_name":"Guoliang Li","orcid":"https://orcid.org/0000-0001-8334-0446"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Guoliang Li","raw_affiliation_strings":["Vastai Technologies, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0001-8334-0446","affiliations":[{"raw_affiliation_string":"Vastai Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013351400","display_name":"Qinfu Yang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Qinfu Yang","raw_affiliation_strings":["Vastai Technologies, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Vastai Technologies, Shanghai, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033880864","display_name":"Krishnendu Chakrabarty","orcid":"https://orcid.org/0000-0003-4475-6435"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnendu Chakrabarty","raw_affiliation_strings":["Duke University, Durham, NC, USA"],"raw_orcid":"https://orcid.org/0000-0003-4475-6435","affiliations":[{"raw_affiliation_string":"Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5025152730"],"corresponding_institution_ids":["https://openalex.org/I170897317"],"apc_list":null,"apc_paid":null,"fwci":1.4143,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.80135345,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"40","issue":"1","first_page":"185","last_page":"198"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8038069009780884},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5136873126029968},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.4945532977581024},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.49167400598526},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.47437697649002075},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47349199652671814},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4478265047073364},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.44489002227783203},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4447270333766937},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.42851221561431885},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.421719491481781},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4108964204788208},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11337405443191528},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07624274492263794}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8038069009780884},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5136873126029968},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.4945532977581024},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.49167400598526},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.47437697649002075},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47349199652671814},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4478265047073364},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.44489002227783203},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4447270333766937},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.42851221561431885},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.421719491481781},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4108964204788208},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11337405443191528},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07624274492263794},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2020.2990832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.2990832","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W767201593","https://openalex.org/W1539006661","https://openalex.org/W1965393465","https://openalex.org/W1969237463","https://openalex.org/W2004363858","https://openalex.org/W2038476033","https://openalex.org/W2109018779","https://openalex.org/W2120890300","https://openalex.org/W2128285650","https://openalex.org/W2143586611","https://openalex.org/W2168675153","https://openalex.org/W2169553754","https://openalex.org/W2403474765","https://openalex.org/W2524658815","https://openalex.org/W2570543678","https://openalex.org/W2781852892","https://openalex.org/W2794493912","https://openalex.org/W2806333336","https://openalex.org/W2806425357","https://openalex.org/W2903844065","https://openalex.org/W2913851478","https://openalex.org/W2988680766","https://openalex.org/W3008494238","https://openalex.org/W3008880067","https://openalex.org/W3146952922","https://openalex.org/W4243047118","https://openalex.org/W4247918850"],"related_works":["https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W1590307681","https://openalex.org/W4312814274","https://openalex.org/W4285370786","https://openalex.org/W2296488620","https://openalex.org/W2358353312","https://openalex.org/W2353836703","https://openalex.org/W41015297","https://openalex.org/W4280645561"],"abstract_inverted_index":{"The":[0],"IEEE":[1],"Std.":[2],"1687":[3],"facilitates":[4],"flexible":[5],"access":[6,23,121],"to":[7,37,69,138,156],"on-chip":[8],"instruments":[9,48],"through":[10,62],"the":[11,18,21,35,42,63,72,111,119,140,158,161],"JTAG":[12],"test-access":[13],"port.":[14],"This":[15],"flexibility":[16],"enables":[17],"minimization":[19],"of":[20,29,54,142,160],"overall":[22],"time":[24,122],"(OAT),":[25],"and":[26,83,132,150],"a":[27,51],"number":[28],"techniques":[30],"have":[31],"been":[32],"proposed":[33,162],"in":[34],"literature":[36],"achieve":[38],"this":[39,58],"goal.":[40],"However,":[41],"OAT":[43],"is":[44,60,93,124,136],"still":[45],"high":[46],"for":[47,86],"that":[49,80,103,118],"require":[50],"large":[52],"amount":[53],"test":[55],"data":[56,59],"if":[57],"shifted":[61],"scan":[64,144],"chain":[65],"serially.":[66],"In":[67,126],"order":[68],"further":[70],"reduce":[71],"OAT,":[73],"we":[74,108],"present":[75],"an":[76,128,133],"efficient":[77,113],"test-scheduling":[78],"method":[79,92,135],"exploits":[81],"broadcast":[82,90],"hardware":[84],"parallelism":[85],"instrument":[87],"access.":[88],"A":[89],"scheduling":[91],"synergistically":[94],"combined":[95],"with":[96],"three":[97,151],"parallel":[98,114],"IJTAG":[99,115,152],"designs.":[100],"We":[101],"show":[102],"under":[104],"different":[105],"cost":[106],"criteria,":[107],"can":[109],"select":[110],"most":[112],"design":[116,131],"such":[117],"equivalent":[120],"(EAT)":[123],"minimized.":[125],"addition,":[127],"interconnect":[129],"fabric":[130],"integer-linear-programming":[134],"used":[137,155],"balance":[139],"lengths":[141],"multiple":[143],"chains.":[145],"Two":[146],"industry":[147],"chip":[148],"designs":[149],"benchmarks":[153],"are":[154],"evaluate":[157],"effectiveness":[159],"method.":[163]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
