{"id":"https://openalex.org/W3008209841","doi":"https://doi.org/10.1109/tcad.2020.2974343","title":"A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs","display_name":"A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs","publication_year":2020,"publication_date":"2020-02-18","ids":{"openalex":"https://openalex.org/W3008209841","doi":"https://doi.org/10.1109/tcad.2020.2974343","mag":"3008209841"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.2974343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.2974343","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024446418","display_name":"Gabriel A. G. Andrade","orcid":"https://orcid.org/0000-0003-2269-7331"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Gabriel A. G. Andrade","raw_affiliation_strings":["Automation and Systems Engineering Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil"],"raw_orcid":"https://orcid.org/0000-0003-2269-7331","affiliations":[{"raw_affiliation_string":"Automation and Systems Engineering Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil","institution_ids":["https://openalex.org/I4104125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036918040","display_name":"Marleson Graf","orcid":"https://orcid.org/0000-0003-3636-1126"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marleson Graf","raw_affiliation_strings":["Computer Science Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil"],"raw_orcid":"https://orcid.org/0000-0003-3636-1126","affiliations":[{"raw_affiliation_string":"Computer Science Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil","institution_ids":["https://openalex.org/I4104125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029601949","display_name":"N\u00edcolas Pfeifer","orcid":"https://orcid.org/0000-0001-8668-181X"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Nicolas Pfeifer","raw_affiliation_strings":["Computer Science Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil"],"raw_orcid":"https://orcid.org/0000-0001-8668-181X","affiliations":[{"raw_affiliation_string":"Computer Science Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil","institution_ids":["https://openalex.org/I4104125"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033216070","display_name":"Luiz C. V. dos Santos","orcid":"https://orcid.org/0000-0002-9384-8347"},"institutions":[{"id":"https://openalex.org/I4104125","display_name":"Universidade Federal de Santa Catarina","ror":"https://ror.org/041akq887","country_code":"BR","type":"education","lineage":["https://openalex.org/I4104125"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luiz C. V. dos Santos","raw_affiliation_strings":["Automation and Systems Engineering Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil","Computer Science Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil"],"raw_orcid":"https://orcid.org/0000-0002-9384-8347","affiliations":[{"raw_affiliation_string":"Automation and Systems Engineering Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil","institution_ids":["https://openalex.org/I4104125"]},{"raw_affiliation_string":"Computer Science Graduate Program, Federal University of Santa Catarina, Florian\u00f3polis, Brazil","institution_ids":["https://openalex.org/I4104125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4104125"],"apc_list":null,"apc_paid":null,"fwci":1.1802,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.76038879,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"39","issue":"12","first_page":"5295","last_page":"5303"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7783856987953186},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.6612223386764526},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6065717339515686},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5557905435562134},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4826972484588623},{"id":"https://openalex.org/keywords/coherence","display_name":"Coherence (philosophical gambling strategy)","score":0.4628976881504059},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.44655081629753113},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44289296865463257},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43972596526145935},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4310379922389984},{"id":"https://openalex.org/keywords/consistency","display_name":"Consistency (knowledge bases)","score":0.4277617931365967},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4161509573459625},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2517373561859131},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10319626331329346},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.09905314445495605}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7783856987953186},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.6612223386764526},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6065717339515686},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5557905435562134},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4826972484588623},{"id":"https://openalex.org/C2781181686","wikidata":"https://www.wikidata.org/wiki/Q4226068","display_name":"Coherence (philosophical gambling strategy)","level":2,"score":0.4628976881504059},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.44655081629753113},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44289296865463257},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43972596526145935},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4310379922389984},{"id":"https://openalex.org/C2776436953","wikidata":"https://www.wikidata.org/wiki/Q5163215","display_name":"Consistency (knowledge bases)","level":2,"score":0.4277617931365967},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4161509573459625},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2517373561859131},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10319626331329346},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.09905314445495605},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2020.2974343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.2974343","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.6600000262260437}],"awards":[{"id":"https://openalex.org/G4223413289","display_name":null,"funder_award_id":"141686/2019-7","funder_id":"https://openalex.org/F4320322025","funder_display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico"}],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"},{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1808398105","https://openalex.org/W1857467995","https://openalex.org/W2029601347","https://openalex.org/W2042831455","https://openalex.org/W2051821475","https://openalex.org/W2064769333","https://openalex.org/W2105945277","https://openalex.org/W2141618784","https://openalex.org/W2147657366","https://openalex.org/W2151460056","https://openalex.org/W2153636750","https://openalex.org/W2157452647","https://openalex.org/W2167118522","https://openalex.org/W2325421623","https://openalex.org/W2605308338","https://openalex.org/W2789870489","https://openalex.org/W2899776668","https://openalex.org/W2914317693","https://openalex.org/W2998350894","https://openalex.org/W3151820404","https://openalex.org/W4235687642","https://openalex.org/W6639420711","https://openalex.org/W6666970197"],"related_works":["https://openalex.org/W17155033","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W1590307681","https://openalex.org/W2536018345","https://openalex.org/W4312814274","https://openalex.org/W4285370786","https://openalex.org/W2296488620","https://openalex.org/W2337418885","https://openalex.org/W4207012101"],"abstract_inverted_index":{"The":[0,78],"functional":[1],"verification":[2],"of":[3,9,35,41,68],"multicore":[4],"chips":[5],"requires":[6],"the":[7,26,33,38,42,69,121,142,153,167,186],"generation":[8,56,62],"parallel":[10],"test":[11,55,61],"programs":[12],"able":[13],"to":[14,111,117,125,148,151,162,165,177,191],"expose":[15],"design":[16],"errors":[17,182],"and":[18,95,116,158],"ensure":[19],"high":[20],"coverage":[21,94,107,127],"in":[22,175],"less":[23],"time.":[24],"Albeit":[25],"coherence":[27,43,70],"hardware":[28],"can":[29],"scale":[30],"gracefully":[31],"as":[32],"number":[34],"cores":[36],"grows,":[37],"state":[39,71],"space":[40,72],"protocol":[44],"increases":[45],"exponentially.":[46],"That":[47],"is":[48,76],"why":[49],"this":[50],"article":[51],"describes":[52],"a":[53,86,96,112,118,180],"directed":[54],"approach":[57,80,123,144],"that":[58,89,99],"exploits":[59,100],"random":[60],"(RTG)":[63],"for":[64,83],"avoiding":[65],"explicit":[66],"enumeration":[67],"while":[73,102],"memory":[74],"consistency":[75],"verified.":[77],"novel":[79,143],"was":[81,145,160],"designed":[82],"synergy":[84],"between":[85],"data-driven":[87,114,154,187],"engine":[88,98],"explores":[90],"neighborhoods":[91],"toward":[92,105],"higher":[93],"model-based":[97,119],"constraints":[101],"driving":[103],"RTG":[104],"faster":[106,150,164],"evolution.":[108],"As":[109],"compared":[110],"state-of-the-art":[113],"generator":[115,188],"generator,":[120],"proposed":[122],"led":[124],"superior":[126],"evolution":[128],"with":[129],"time,":[130],"when":[131],"targeting":[132],"32-core":[133],"designs":[134],"relying":[135],"on":[136],"different":[137],"protocols.":[138],"For":[139,170],"MOESI":[140],"2-level,":[141],"from":[146],"4.8":[147],"18.7":[149],"reach":[152,166],"generator's":[155],"maximal":[156],"coverage,":[157],"it":[159,173],"up":[161],"2.7":[163],"model-driven":[168],"generator's.":[169],"MESI":[171],"3-level,":[172],"found,":[174],"10":[176],"15":[178],"min,":[179],"few":[181],"whose":[183],"detection":[184],"required":[185],"45":[189],"min":[190],"7":[192],"h.":[193]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}