{"id":"https://openalex.org/W2774510317","doi":"https://doi.org/10.1109/tcad.2020.2968892","title":"Clock-Aware Placement for Large-Scale Heterogeneous FPGAs","display_name":"Clock-Aware Placement for Large-Scale Heterogeneous FPGAs","publication_year":2020,"publication_date":"2020-01-23","ids":{"openalex":"https://openalex.org/W2774510317","doi":"https://doi.org/10.1109/tcad.2020.2968892","mag":"2774510317"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2020.2968892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.2968892","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113333659","display_name":"Jianli Chen","orcid":"https://orcid.org/0000-0002-5843-0674"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":["Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, China","State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5843-0674","affiliations":[{"raw_affiliation_string":"Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]},{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101664594","display_name":"Zhifeng Lin","orcid":"https://orcid.org/0000-0002-4597-4322"},"institutions":[{"id":"https://openalex.org/I80947539","display_name":"Fuzhou University","ror":"https://ror.org/011xvna82","country_code":"CN","type":"education","lineage":["https://openalex.org/I80947539"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhifeng Lin","raw_affiliation_strings":["College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China","institution_ids":["https://openalex.org/I80947539"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066038907","display_name":"Yun-Chih Kuo","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148979","display_name":"MediaTek (Taiwan)","ror":"https://ror.org/05g9jck81","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210148979"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yun-Chih Kuo","raw_affiliation_strings":["MediaTek, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MediaTek, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148979"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032624921","display_name":"Chau-Chin Huang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chau-Chin Huang","raw_affiliation_strings":["Synopsys, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yao-Wen Chang","orcid":"https://orcid.org/0000-0001-8838-2653"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan","Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":"https://orcid.org/0000-0001-8838-2653","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035783996","display_name":"Shih-Chun Chen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shih-Chun Chen","raw_affiliation_strings":["Synopsys, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072742686","display_name":"Chun-Han Chiang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Han Chiang","raw_affiliation_strings":["Synopsys, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043885374","display_name":"Sy\u2010Yen Kuo","orcid":"https://orcid.org/0000-0002-3021-8321"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sy-Yen Kuo","raw_affiliation_strings":["Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan","Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-3021-8321","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.817,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.85000486,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"39","issue":"12","first_page":"5042","last_page":"5055"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8119126558303833},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7478735446929932},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5235742330551147},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48718971014022827},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4770340621471405},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.471723735332489},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.46668893098831177},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4532011151313782},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.42602866888046265},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38575491309165955},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.0795971155166626}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8119126558303833},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7478735446929932},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5235742330551147},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48718971014022827},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4770340621471405},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.471723735332489},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.46668893098831177},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4532011151313782},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.42602866888046265},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38575491309165955},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0795971155166626},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2020.2968892","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2020.2968892","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16","score":0.4399999976158142}],"awards":[{"id":"https://openalex.org/G1417091005","display_name":null,"funder_award_id":"MOST 104-2221-E-002-132-MY3","funder_id":"https://openalex.org/F4320322410","funder_display_name":"MediaTek"},{"id":"https://openalex.org/G2991555010","display_name":null,"funder_award_id":"MOST 105-2221-E-002-190-MY3","funder_id":"https://openalex.org/F4320322410","funder_display_name":"MediaTek"},{"id":"https://openalex.org/G4126065796","display_name":null,"funder_award_id":"MOST 106-2911-I-002-511","funder_id":"https://openalex.org/F4320322410","funder_display_name":"MediaTek"},{"id":"https://openalex.org/G7246040965","display_name":null,"funder_award_id":"MOST 103-2221-E-002-259-MY3","funder_id":"https://openalex.org/F4320322410","funder_display_name":"MediaTek"},{"id":"https://openalex.org/G7794251492","display_name":null,"funder_award_id":"MOST 106-2221-E-002-203-MY3","funder_id":"https://openalex.org/F4320322410","funder_display_name":"MediaTek"},{"id":"https://openalex.org/G8025620321","display_name":null,"funder_award_id":"NTU-ERP-104R8951","funder_id":"https://openalex.org/F4320323900","funder_display_name":"National Taiwan University"},{"id":"https://openalex.org/G8355911810","display_name":null,"funder_award_id":"NTU-ERP-105R8951","funder_id":"https://openalex.org/F4320323900","funder_display_name":"National Taiwan University"}],"funders":[{"id":"https://openalex.org/F4320322410","display_name":"MediaTek","ror":"https://ror.org/05g9jck81"},{"id":"https://openalex.org/F4320323900","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W2002641171","https://openalex.org/W2004122330","https://openalex.org/W2020461489","https://openalex.org/W2020549672","https://openalex.org/W2021149030","https://openalex.org/W2029031086","https://openalex.org/W2031974129","https://openalex.org/W2055251702","https://openalex.org/W2058324481","https://openalex.org/W2067856828","https://openalex.org/W2075137913","https://openalex.org/W2114136290","https://openalex.org/W2114871550","https://openalex.org/W2124537194","https://openalex.org/W2137454730","https://openalex.org/W2138206217","https://openalex.org/W2139637699","https://openalex.org/W2146232231","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2154014710","https://openalex.org/W2154302973","https://openalex.org/W2165419774","https://openalex.org/W2167190617","https://openalex.org/W2278433511","https://openalex.org/W2516919812","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2538165366","https://openalex.org/W2595334824","https://openalex.org/W2771551340","https://openalex.org/W2801898382","https://openalex.org/W2886700560","https://openalex.org/W2915733502","https://openalex.org/W4234143391","https://openalex.org/W4245688993","https://openalex.org/W4249211602","https://openalex.org/W4252122657","https://openalex.org/W6655577606","https://openalex.org/W6676886990","https://openalex.org/W6680484343"],"related_works":["https://openalex.org/W4247089581","https://openalex.org/W2174922170","https://openalex.org/W3006003651","https://openalex.org/W331180034","https://openalex.org/W1596690381","https://openalex.org/W2088914741","https://openalex.org/W2133326759","https://openalex.org/W2559451387","https://openalex.org/W4247180033","https://openalex.org/W2011677428"],"abstract_inverted_index":{"A":[0],"modern":[1],"field-programmable":[2],"gate":[3],"array":[4],"(FPGA)":[5],"often":[6],"contains":[7],"an":[8,48,119,137],"ASIC-like":[9],"clocking":[10,28,43,77],"architecture":[11],"which":[12],"is":[13],"crucial":[14],"to":[15,34,71,85,89,97,108,117,135],"achieve":[16],"better":[17],"skew":[18],"and":[19,30,92,112,126,132],"performance.":[20],"Existing":[21],"conventional":[22],"FPGA":[23,42],"placement":[24,51,110,124],"algorithms":[25],"seldom":[26],"consider":[27],"resources,":[29],"thus":[31],"may":[32],"lead":[33,86],"clock":[35,67],"routing":[36],"failures.":[37],"To":[38],"address":[39],"the":[40,74,122,147,157,160,168],"special":[41],"architecture,":[44],"this":[45],"article":[46],"presents":[47],"effective":[49],"clock-aware":[50,130],"algorithm":[52,58,107,166],"for":[53],"large-scale":[54],"heterogeneous":[55,82,87,104],"FPGAs.":[56],"Our":[57],"consists":[59],"of":[60,76,121],"four":[61],"major":[62],"technologies:":[63],"1)":[64],"a":[65,80,93,103,113,128],"combinatorial":[66],"fence":[68],"region":[69],"method":[70],"effectively":[72],"reduce":[73],"overuse":[75],"resources;":[78],"2)":[79],"smoothed":[81],"density":[83],"function":[84],"blocks":[88],"desired":[90],"sites":[91],"coordinate":[94],"transformation":[95],"technique":[96,116],"facilitate":[98],"CLB":[99],"cell":[100],"spreading;":[101],"3)":[102],"force":[105],"modulation":[106],"stabilize":[109],"movement":[111],"hierarchical":[114],"contraction":[115],"remedy":[118],"insufficiency":[120],"multilevel":[123],"framework;":[125],"4)":[127],"two-level":[129],"packing":[131],"legalization":[133],"scheme":[134],"generate":[136],"optimized,":[138],"clocking-violation-free":[139],"placement.":[140],"We":[141],"evaluate":[142],"our":[143,165],"results":[144,162],"based":[145],"on":[146],"ISPD":[148],"2017":[149],"Clock-Aware":[150],"Placement":[151],"Contest":[152],"benchmark":[153],"suite.":[154],"Compared":[155],"with":[156],"state-of-the-art":[158],"placers,":[159],"experimental":[161],"show":[163],"that":[164],"achieves":[167],"best-routed":[169],"wirelength.":[170]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}