{"id":"https://openalex.org/W2962820765","doi":"https://doi.org/10.1109/tcad.2019.2931185","title":"Physically Aware Affinity-Driven Multiplier Implementation","display_name":"Physically Aware Affinity-Driven Multiplier Implementation","publication_year":2019,"publication_date":"2019-07-25","ids":{"openalex":"https://openalex.org/W2962820765","doi":"https://doi.org/10.1109/tcad.2019.2931185","mag":"2962820765"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2019.2931185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2931185","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024705445","display_name":"Or Maltabashi","orcid":"https://orcid.org/0000-0002-6833-0829"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":true,"raw_author_name":"Or Maltabashi","raw_affiliation_strings":["Emerging Nanoscale Integrated Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":"https://orcid.org/0000-0002-6833-0829","affiliations":[{"raw_affiliation_string":"Emerging Nanoscale Integrated Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053686269","display_name":"Yehuda Kra","orcid":"https://orcid.org/0009-0002-3377-6529"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Yehuda Kra","raw_affiliation_strings":["Emerging Nanoscale Integrated Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Emerging Nanoscale Integrated Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026444183","display_name":"Adam Teman","orcid":"https://orcid.org/0000-0002-8233-4711"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Adam Teman","raw_affiliation_strings":["Emerging Nanoscale Integrated Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":"https://orcid.org/0000-0002-8233-4711","affiliations":[{"raw_affiliation_string":"Emerging Nanoscale Integrated Circuits and Systems Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5024705445"],"corresponding_institution_ids":["https://openalex.org/I13955877"],"apc_list":null,"apc_paid":null,"fwci":0.2421,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.54991884,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"39","issue":"10","first_page":"2886","last_page":"2897"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9024356007575989},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7322443723678589},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.7092714905738831},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.6615499258041382},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.4897034466266632},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4896462559700012},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.47737619280815125},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.47192835807800293},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4707907736301422},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4631573259830475},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45622310042381287},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.428347110748291},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4281430244445801},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.423724889755249},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.418770968914032},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.41067826747894287},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38616761565208435},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3136295676231384},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29302525520324707},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2745453119277954},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27426958084106445},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24772891402244568},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.15872904658317566},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13212499022483826},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1138569712638855}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9024356007575989},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7322443723678589},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.7092714905738831},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.6615499258041382},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4897034466266632},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4896462559700012},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.47737619280815125},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.47192835807800293},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4707907736301422},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4631573259830475},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45622310042381287},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.428347110748291},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4281430244445801},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.423724889755249},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.418770968914032},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.41067826747894287},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38616761565208435},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3136295676231384},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29302525520324707},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2745453119277954},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27426958084106445},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24772891402244568},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.15872904658317566},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13212499022483826},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1138569712638855},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2019.2931185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2931185","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1561781055","https://openalex.org/W1983849809","https://openalex.org/W2053276728","https://openalex.org/W2094575947","https://openalex.org/W2110025685","https://openalex.org/W2119912171","https://openalex.org/W2157024459","https://openalex.org/W2462499937","https://openalex.org/W2517484775","https://openalex.org/W2552747325","https://openalex.org/W2559579271","https://openalex.org/W2583382730","https://openalex.org/W2592389822","https://openalex.org/W2594836184","https://openalex.org/W2606722458","https://openalex.org/W2787816752","https://openalex.org/W2808739938"],"related_works":["https://openalex.org/W4288055011","https://openalex.org/W2100360214","https://openalex.org/W3209275736","https://openalex.org/W2889102485","https://openalex.org/W4245336546","https://openalex.org/W2038511870","https://openalex.org/W3047211184","https://openalex.org/W2070693700","https://openalex.org/W2543084892","https://openalex.org/W4386859294"],"abstract_inverted_index":{"Optimized":[0],"hardware":[1],"for":[2],"the":[3,25,58,67,70,74,94,97,103,113],"execution":[4],"of":[5,14,57,69,77,151],"large":[6,79],"dot-product":[7],"(DP)":[8],"calculations":[9,133],"is":[10],"central":[11],"to":[12,32,63,89,118,124,136,153,156,169],"many":[13],"today's":[15],"integrated":[16],"circuits.":[17,80],"These":[18],"arithmetic":[19],"blocks":[20],"are":[21,36,52],"often":[22],"implemented":[23,140],"with":[24,38,121,134,141],"parallel":[26],"fused":[27],"DP":[28,109,132],"(FDP)":[29],"approach,":[30],"and":[31,61,115,128,160],"achieve":[33],"high":[34,164],"performance,":[35],"realized":[37],"a":[39,86,142],"tree-based":[40],"compression":[41],"algorithm,":[42,111],"using":[43],"on":[44,54,73,93,173,177],"commercially":[45],"available":[46],"synthesis":[47],"macros.":[48],"However,":[49],"these":[50,78],"macros":[51,175],"based":[53,92,172,176],"performance":[55,161],"optimization":[56],"gate-level":[59,104],"netlist,":[60],"fail":[62],"take":[64],"into":[65],"account":[66],"consequences":[68],"applied":[71],"heuristics":[72],"physical-implementation":[75],"(layout)":[76],"In":[81],"this":[82],"article,":[83],"we":[84],"propose":[85],"physical-aware":[87],"approach":[88],"FDP":[90],"implementation":[91],"affinity":[95],"between":[96],"logic":[98],"gates":[99,120],"that":[100],"make":[101],"up":[102,135,152,155],"structure.":[105],"The":[106],"proposed":[107],"clustered":[108],"(CDP)":[110],"enables":[112],"place":[114],"route":[116],"tools":[117],"cluster":[119],"high-affinity,":[122],"leading":[123],"higher":[125],"placement":[126],"utilization":[127],"lower":[129,158],"routing":[130],"congestion.":[131],"78":[137],"multipliers":[138],"were":[139],"65-nm":[143],"CMOS":[144],"standard":[145],"cell":[146],"library,":[147],"providing":[148],"power":[149],"reduction":[150],"63%,":[154],"60%":[157],"area,":[159],"improvements":[162],"as":[163,165,167],"2.5\u00d7,":[166],"compared":[168],"similar":[170],"implementations":[171],"commercial":[174],"post-layout":[178],"results.":[179]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}