{"id":"https://openalex.org/W2969852599","doi":"https://doi.org/10.1109/tcad.2019.2921345","title":"Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run","display_name":"Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run","publication_year":2019,"publication_date":"2019-06-06","ids":{"openalex":"https://openalex.org/W2969852599","doi":"https://doi.org/10.1109/tcad.2019.2921345","mag":"2969852599"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2019.2921345","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2921345","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019488876","display_name":"Yi-Cheng Kung","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yi-Cheng Kung","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079657769","display_name":"Kuen-Jong Lee","orcid":"https://orcid.org/0000-0002-6690-0074"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kuen-Jong Lee","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077101123","display_name":"S.M. Reddy","orcid":"https://orcid.org/0000-0001-9208-8262"},"institutions":[{"id":"https://openalex.org/I126307644","display_name":"University of Iowa","ror":"https://ror.org/036jqmy94","country_code":"US","type":"education","lineage":["https://openalex.org/I126307644"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar M. Reddy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Iowa, Iowa City, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Iowa, Iowa City, USA","institution_ids":["https://openalex.org/I126307644"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5019488876"],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":0.9631,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.73832507,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"39","issue":"6","first_page":"1340","last_page":"1345"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.9157108068466187},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6785510182380676},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6225978136062622},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.5535582900047302},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5466183423995972},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.5187278389930725},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.4976048767566681},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4804129898548126},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4679754078388214},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4646081328392029},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.44441455602645874},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3446512818336487},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3392940163612366},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33194446563720703},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32270899415016174},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.2792951166629791},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12429335713386536},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09760111570358276}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.9157108068466187},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6785510182380676},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6225978136062622},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.5535582900047302},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5466183423995972},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.5187278389930725},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.4976048767566681},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4804129898548126},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4679754078388214},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4646081328392029},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.44441455602645874},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3446512818336487},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3392940163612366},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33194446563720703},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32270899415016174},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.2792951166629791},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12429335713386536},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09760111570358276},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2019.2921345","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2921345","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5602002309","display_name":null,"funder_award_id":"MOST 107-2218-E-006-025","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"}],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1849928240","https://openalex.org/W1971601082","https://openalex.org/W2015281050","https://openalex.org/W2032155184","https://openalex.org/W2036584993","https://openalex.org/W2070302634","https://openalex.org/W2093474179","https://openalex.org/W2096146619","https://openalex.org/W2101637552","https://openalex.org/W2118744758","https://openalex.org/W2122054055","https://openalex.org/W2148271311","https://openalex.org/W2148650495","https://openalex.org/W2149147759","https://openalex.org/W2158401235","https://openalex.org/W2163558178","https://openalex.org/W2171020103","https://openalex.org/W2911501307","https://openalex.org/W4247981882","https://openalex.org/W6673776565"],"related_works":["https://openalex.org/W2340957901","https://openalex.org/W4256030018","https://openalex.org/W2147400189","https://openalex.org/W3147038789","https://openalex.org/W2068571131","https://openalex.org/W1555400249","https://openalex.org/W2115005577","https://openalex.org/W2092357065","https://openalex.org/W2913077774","https://openalex.org/W2952274626"],"abstract_inverted_index":{"A":[0],"novel":[1],"test":[2,95],"pattern":[3],"generation":[4],"method":[5,114],"for":[6,74],"multiple":[7],"dc":[8,76],"and":[9,23,77,93,104],"ac":[10,78],"faults":[11,28,33,47,79],"is":[12],"presented.":[13],"The":[14,99],"fault":[15,54],"models":[16],"considered":[17,46],"include":[18],"line":[19],"stuck-at,":[20],"bridging,":[21],"transition,":[22],"transistor":[24],"stuck-open":[25],"faults.":[26],"All":[27],"are":[29,97],"transformed":[30],"into":[31],"stuck-at":[32],"with":[34],"some":[35],"constraints":[36],"in":[37,80],"the":[38,52,88,109,112],"proposed":[39,113],"two-timeframe":[40],"circuit":[41],"model":[42,55],"such":[43],"that":[44],"all":[45],"can":[48],"be":[49],"represented":[50],"utilizing":[51],"user-defined":[53],"supported":[56],"currently":[57],"by":[58],"most":[59],"commercial":[60],"ATPG":[61,82,89],"tools.":[62],"This":[63],"makes":[64],"it":[65],"possible":[66],"to":[67,86,117],"generate":[68],"a":[69],"compact":[70],"set":[71],"of":[72,111],"patterns":[73],"both":[75],"one":[81],"run":[83],"without":[84],"needing":[85],"modify":[87],"tool.":[90],"Both":[91],"launch-on-capture":[92],"launch-on-shift":[94],"methods":[96],"supported.":[98],"experimental":[100],"results":[101],"on":[102],"ISCAS'89":[103],"ITC'99":[105],"benchmark":[106],"circuits":[107],"show":[108],"effectiveness":[110],"(PM)":[115],"compared":[116],"earlier":[118],"PMs.":[119]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":8},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}