{"id":"https://openalex.org/W2942072122","doi":"https://doi.org/10.1109/tcad.2019.2912933","title":"Automatic Generation of Differential-Input Differential-Output Second-Order Filters Based on a Differential Pair","display_name":"Automatic Generation of Differential-Input Differential-Output Second-Order Filters Based on a Differential Pair","publication_year":2019,"publication_date":"2019-04-25","ids":{"openalex":"https://openalex.org/W2942072122","doi":"https://doi.org/10.1109/tcad.2019.2912933","mag":"2942072122"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2019.2912933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2912933","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014136577","display_name":"Brent Maundy","orcid":"https://orcid.org/0000-0002-3924-2897"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Brent J. Maundy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada"],"raw_orcid":"https://orcid.org/0000-0002-3924-2897","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039814573","display_name":"Ahmed S. Elwakil","orcid":"https://orcid.org/0000-0002-3972-5434"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]},{"id":"https://openalex.org/I29891158","display_name":"University of Sharjah","ror":"https://ror.org/00engpz63","country_code":"AE","type":"education","lineage":["https://openalex.org/I29891158"]}],"countries":["AE","CA"],"is_corresponding":false,"raw_author_name":"Ahmed S. Elwakil","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada","Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, UAE"],"raw_orcid":"https://orcid.org/0000-0002-3972-5434","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, UAE","institution_ids":["https://openalex.org/I29891158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025866057","display_name":"Leonid Belostotski","orcid":"https://orcid.org/0000-0002-5228-6907"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Leonid Belostotski","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada"],"raw_orcid":"https://orcid.org/0000-0002-5228-6907","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0508,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.76998699,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"39","issue":"6","first_page":"1258","last_page":"1271"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5560629367828369},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.5248996019363403},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4736129939556122},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.43975746631622314},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4385480284690857},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41462916135787964},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.4120224714279175},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.41164618730545044},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3590105175971985},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19154083728790283},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17878109216690063},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07671919465065002}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5560629367828369},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.5248996019363403},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4736129939556122},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.43975746631622314},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4385480284690857},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41462916135787964},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.4120224714279175},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.41164618730545044},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3590105175971985},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19154083728790283},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17878109216690063},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07671919465065002},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2019.2912933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2912933","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3442905111","display_name":null,"funder_award_id":"RGPIN-2014-05653","funder_id":"https://openalex.org/F4320334593","funder_display_name":"Natural Sciences and Engineering Research Council of Canada"}],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W69949976","https://openalex.org/W656787519","https://openalex.org/W1566916904","https://openalex.org/W1865663301","https://openalex.org/W1891978801","https://openalex.org/W1974432651","https://openalex.org/W2027765013","https://openalex.org/W2042418076","https://openalex.org/W2048514579","https://openalex.org/W2078269407","https://openalex.org/W2099549006","https://openalex.org/W2108092549","https://openalex.org/W2109000084","https://openalex.org/W2113165532","https://openalex.org/W2123516260","https://openalex.org/W2124927125","https://openalex.org/W2127140695","https://openalex.org/W2132815521","https://openalex.org/W2136284655","https://openalex.org/W2138889413","https://openalex.org/W2138925938","https://openalex.org/W2291880745","https://openalex.org/W2330375287","https://openalex.org/W2495323230","https://openalex.org/W2741530370","https://openalex.org/W2789306143","https://openalex.org/W2796863645","https://openalex.org/W2890928664","https://openalex.org/W2893313719","https://openalex.org/W2899469393","https://openalex.org/W4300356733","https://openalex.org/W6602790465"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W2753223082","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W3025119703","https://openalex.org/W4306968100","https://openalex.org/W4387941415","https://openalex.org/W2347757802","https://openalex.org/W600655143"],"abstract_inverted_index":{"In":[0,57],"this":[1],"paper,":[2],"the":[3,28,43,91,103],"generation":[4],"of":[5,30,47,65,82,118],"differential-input":[6],"differential-output":[7],"second-order":[8],"active":[9],"filters":[10,52,67,107,120],"based":[11],"on":[12,90],"a":[13,37,63,76,127],"common-source":[14],"differential":[15],"amplifier":[16],"is":[17,95,121],"systematically":[18],"conducted":[19],"using":[20,113,126],"two-port":[21],"network":[22],"modeling":[23],"techniques":[24],"which":[25],"enable":[26],"exploiting":[27],"power":[29],"symbolic":[31],"math":[32],"CAD":[33],"tools.":[34],"Starting":[35],"from":[36],"generic":[38],"two-transistor":[39],"differential-pair":[40],"structure,":[41],"and":[42,55,62,97,110],"maximum":[44],"possible":[45,51],"number":[46],"surrounding":[48],"impedances,":[49],"all":[50],"are":[53,68,108],"derived":[54,92],"classified.":[56],"particular,":[58],"35":[59],"transfer":[60,93],"functions":[61,94],"total":[64],"876":[66],"found":[69],"to":[70,74],"be":[71,99],"possible.":[72],"Due":[73],"employing":[75],"$2\\times":[77],"2$":[78],"transmission":[79],"matrix":[80],"representation":[81],"each":[83],"transistor,":[84],"flexibility":[85],"in":[86],"examining":[87],"parasitic":[88],"effects":[89],"achieved":[96],"can":[98],"easily":[100],"automated":[101],"within":[102],"design":[104],"framework.":[105],"Selected":[106],"constructed":[109],"experimentally":[111],"verified":[112,123],"discrete":[114],"transistors.":[115],"The":[116],"operation":[117],"some":[119],"also":[122],"with":[124],"simulations":[125],"65-nm":[128],"CMOS":[129],"process.":[130]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
