{"id":"https://openalex.org/W2926260636","doi":"https://doi.org/10.1109/tcad.2019.2907905","title":"Automating the Design of Asynchronous Logic Control for AMS Electronics","display_name":"Automating the Design of Asynchronous Logic Control for AMS Electronics","publication_year":2019,"publication_date":"2019-03-27","ids":{"openalex":"https://openalex.org/W2926260636","doi":"https://doi.org/10.1109/tcad.2019.2907905","mag":"2926260636"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2019.2907905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2907905","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015272875","display_name":"Danil Sokolov","orcid":"https://orcid.org/0000-0002-4030-0089"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Danil Sokolov","raw_affiliation_strings":["School of Engineering, Newcastle University, Newcastle upon Tyne, U.K"],"raw_orcid":"https://orcid.org/0000-0002-4030-0089","affiliations":[{"raw_affiliation_string":"School of Engineering, Newcastle University, Newcastle upon Tyne, U.K","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008744860","display_name":"Victor Khomenko","orcid":"https://orcid.org/0000-0001-6422-2006"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Victor Khomenko","raw_affiliation_strings":["School of Computing, Newcastle University, Newcastle upon Tyne, U.K"],"raw_orcid":"https://orcid.org/0000-0001-6422-2006","affiliations":[{"raw_affiliation_string":"School of Computing, Newcastle University, Newcastle upon Tyne, U.K","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041019594","display_name":"Andrey Mokhov","orcid":"https://orcid.org/0000-0002-2493-3177"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andrey Mokhov","raw_affiliation_strings":["School of Engineering, Newcastle University, Newcastle upon Tyne, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering, Newcastle University, Newcastle upon Tyne, U.K","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066547919","display_name":"Vladimir Dubikhin","orcid":"https://orcid.org/0000-0003-3843-3541"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Vladimir Dubikhin","raw_affiliation_strings":["School of Engineering, Newcastle University, Newcastle upon Tyne, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering, Newcastle University, Newcastle upon Tyne, U.K","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032944659","display_name":"David G. Lloyd","orcid":"https://orcid.org/0000-0002-0824-9682"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Lloyd","raw_affiliation_strings":["Dialog Semiconductor, Swindon, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dialog Semiconductor, Swindon, U.K","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029446985","display_name":"Alex Yakovlev","orcid":"https://orcid.org/0000-0003-0826-9330"},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Alex Yakovlev","raw_affiliation_strings":["School of Engineering, Newcastle University, Newcastle upon Tyne, U.K"],"raw_orcid":"https://orcid.org/0000-0003-0826-9330","affiliations":[{"raw_affiliation_string":"School of Engineering, Newcastle University, Newcastle upon Tyne, U.K","institution_ids":["https://openalex.org/I84884186"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2843,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.80151932,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"39","issue":"5","first_page":"952","last_page":"965"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7346515655517578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6490828394889832},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6351994276046753},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5815291404724121},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.549353301525116},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4909529983997345},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48072245717048645},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.4439471662044525},{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.430331826210022},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.417594313621521},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33389848470687866},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29476580023765564},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2813637852668762},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.26132339239120483},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21802207827568054},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.18060222268104553}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7346515655517578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6490828394889832},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6351994276046753},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5815291404724121},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.549353301525116},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4909529983997345},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48072245717048645},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.4439471662044525},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.430331826210022},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.417594313621521},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33389848470687866},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29476580023765564},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2813637852668762},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.26132339239120483},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21802207827568054},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.18060222268104553},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2019.2907905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2907905","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:eprint.ncl.ac.uk:255710","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306402485","display_name":"Newcastle University ePrints (Newcastle Univesity)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I84884186","host_organization_name":"Newcastle University","host_organization_lineage":["https://openalex.org/I84884186"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1562502800","display_name":null,"funder_award_id":"EP/L025507/1","funder_id":"https://openalex.org/F4320334593","funder_display_name":"Natural Sciences and Engineering Research Council of Canada"},{"id":"https://openalex.org/G6143952702","display_name":null,"funder_award_id":"EP/L025507/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320320295","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":49,"referenced_works":["https://openalex.org/W34675824","https://openalex.org/W144037624","https://openalex.org/W149082927","https://openalex.org/W1491190094","https://openalex.org/W1491226430","https://openalex.org/W1543804358","https://openalex.org/W1554812212","https://openalex.org/W1565620212","https://openalex.org/W1574570499","https://openalex.org/W1578887748","https://openalex.org/W1590223305","https://openalex.org/W1665361481","https://openalex.org/W1889218533","https://openalex.org/W1996109622","https://openalex.org/W2003685153","https://openalex.org/W2010800225","https://openalex.org/W2016259411","https://openalex.org/W2029005287","https://openalex.org/W2033724727","https://openalex.org/W2041927045","https://openalex.org/W2054242451","https://openalex.org/W2106316647","https://openalex.org/W2108395463","https://openalex.org/W2117648153","https://openalex.org/W2120119834","https://openalex.org/W2124109386","https://openalex.org/W2136676362","https://openalex.org/W2156849124","https://openalex.org/W2160823654","https://openalex.org/W2340714136","https://openalex.org/W2487142227","https://openalex.org/W2548635540","https://openalex.org/W2560771452","https://openalex.org/W2594560887","https://openalex.org/W2626777862","https://openalex.org/W2632267592","https://openalex.org/W2742171493","https://openalex.org/W2752037999","https://openalex.org/W2768050347","https://openalex.org/W4211171470","https://openalex.org/W4233328302","https://openalex.org/W4246084264","https://openalex.org/W6605785886","https://openalex.org/W6629326351","https://openalex.org/W6633282629","https://openalex.org/W6637168539","https://openalex.org/W6683394555","https://openalex.org/W6739806715","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W2548837243","https://openalex.org/W1984298705","https://openalex.org/W4256596352","https://openalex.org/W4244147444","https://openalex.org/W2154582989","https://openalex.org/W2093491063","https://openalex.org/W2161215820","https://openalex.org/W2086539401","https://openalex.org/W4241462776","https://openalex.org/W2919987885"],"abstract_inverted_index":{"Analog":[0],"and":[1,9,36,59,73,88,99,132,170,174,188,209,216],"mixed":[2],"signal":[3],"(AMS)":[4],"electronics":[5,66],"becomes":[6],"increasingly":[7],"complex":[8],"needs":[10],"to":[11,113,130,134,181,212],"be":[12,190],"digitally":[13],"enhanced":[14],"by":[15],"its":[16],"own":[17],"control":[18,39,123],"circuitry.":[19],"The":[20,158],"RTL":[21],"synthesis":[22],"flow":[23,68,92,208],"routinely":[24],"used":[25],"for":[26,32,40,64,69,85,193],"digital":[27],"logic":[28],"is,":[29],"however,":[30],"optimized":[31],"synchronous":[33],"data":[34],"processing":[35],"produces":[37],"inefficient":[38],"AMS.":[41],"In":[42],"this":[43],"paper,":[44],"we":[45],"demonstrate":[46,166],"the":[47,54,96,182,194,202,205],"evident":[48],"benefits":[49,179],"of":[50,56,78,120,161,185,196,204,219],"asynchronous":[51,62,89,121,164],"circuits":[52],"in":[53,95],"context":[55],"AMS":[57,220],"systems,":[58],"propose":[60],"an":[61],"design":[63,207,214],"analog":[65,87,115,197],"(A4A)":[67],"their":[70],"specification,":[71],"synthesis,":[72],"formal":[74],"verification.":[75],"A":[76],"library":[77],"specialized":[79],"analog-to-asynchronous":[80],"(A2A)":[81],"components":[82,110],"is":[83,93],"developed":[84],"interfacing":[86],"worlds.":[90],"A4A":[91],"automated":[94],"Workcraft":[97],"framework":[98],"evaluated":[100],"using":[101],"a":[102,139,146,150,162],"multiphase":[103],"buck":[104,122,165],"converter":[105],"case":[106],"study,":[107],"where":[108],"A2A":[109],"are":[111],"employed":[112],"sanitize":[114],"sensor":[116],"readings.":[117],"Timing":[118],"analysis":[119],"shows":[124],"improved":[125,167],"response":[126,148],"time:":[127],"4\u00d7":[128],"reaction":[129],"high-load":[131],"7\u00d7":[133],"under-voltage":[135],"condition,":[136],"compared":[137],"with":[138],"333":[140],"MHz":[141],"clocked":[142,151],"controller":[143,152],"(to":[144],"achieve":[145],"similar":[147],"time,":[149],"would":[153],"require":[154],"~3":[155],"GHz":[156],"frequency).":[157],"simulation":[159],"results":[160],"4-phase":[163],"voltage":[168],"ripple":[169],"peak":[171],"current":[172],"-16%":[173],"12%":[175],"reduction,":[176],"respectively.":[177],"These":[178],"lead":[180],"higher":[183],"efficiency":[184],"power":[186],"conversion,":[187],"can":[189],"traded":[191],"off":[192],"cost":[195],"components,":[198],"e.g.,":[199],"coils.":[200],"Moreover,":[201],"use":[203],"proposed":[206],"tools":[210],"helps":[211],"improve":[213],"productivity":[215],"overall":[217],"robustness":[218],"circuits.":[221]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}