{"id":"https://openalex.org/W2925003042","doi":"https://doi.org/10.1109/tcad.2019.2907879","title":"A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping","display_name":"A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping","publication_year":2019,"publication_date":"2019-03-27","ids":{"openalex":"https://openalex.org/W2925003042","doi":"https://doi.org/10.1109/tcad.2019.2907879","mag":"2925003042"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2019.2907879","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2907879","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"preprint","indexed_in":["arxiv","crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/1903.11264","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090084197","display_name":"Sitansusekhar Roymohapatra","orcid":"https://orcid.org/0000-0002-5488-7183"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sitansusekhar Roymohapatra","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India"],"raw_orcid":"https://orcid.org/0000-0002-5488-7183","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006420890","display_name":"Ganesh Gore","orcid":"https://orcid.org/0000-0002-0310-197X"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]},{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Ganesh R. Gore","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology, Bombay, India","Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, USA","Department of Electrical Engineering, Indian institute of Technology, Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, USA","institution_ids":["https://openalex.org/I223532165"]},{"raw_affiliation_string":"Department of Electrical Engineering, Indian institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025644834","display_name":"Akanksha Yadav","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Akanksha Yadav","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101943503","display_name":"Mahesh B. Patil","orcid":"https://orcid.org/0000-0001-8766-1044"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mahesh B. Patil","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India"],"raw_orcid":"https://orcid.org/0000-0001-8766-1044","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036909129","display_name":"Krishnan S. Rengarajan","orcid":"https://orcid.org/0000-0001-5967-3005"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Krishnan S. Rengarajan","raw_affiliation_strings":["Cypress Semiconductor Corporation (India), Bengaluru, India","Globalfoundries (India), Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cypress Semiconductor Corporation (India), Bengaluru, India","institution_ids":[]},{"raw_affiliation_string":"Globalfoundries (India), Bengaluru, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Subramanian S. Iyer","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subramanian S. Iyer","raw_affiliation_strings":["Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, USA","Department of Electrical Engineering, University of California at Los Angeles , Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, USA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Department of Electrical Engineering, University of California at Los Angeles , Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029767607","display_name":"Maryam Shojaei Baghini","orcid":"https://orcid.org/0000-0001-6568-3736"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Maryam Shojaei Baghini","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India"],"raw_orcid":"https://orcid.org/0000-0001-6568-3736","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01970072,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"39","issue":"5","first_page":"1073","last_page":"1083"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.908325731754303},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7243878245353699},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6112686395645142},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.5570343136787415},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.542691707611084},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4274849593639374},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.41871410608291626},{"id":"https://openalex.org/keywords/electronic-circuit-simulation","display_name":"Electronic circuit simulation","score":0.411479651927948},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36862054467201233},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3244517147541046},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.24366968870162964},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2413138747215271},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1422327756881714},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12416070699691772},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11070266366004944}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.908325731754303},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7243878245353699},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6112686395645142},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.5570343136787415},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.542691707611084},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4274849593639374},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.41871410608291626},{"id":"https://openalex.org/C46205389","wikidata":"https://www.wikidata.org/wiki/Q1270401","display_name":"Electronic circuit simulation","level":3,"score":0.411479651927948},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36862054467201233},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3244517147541046},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.24366968870162964},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2413138747215271},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1422327756881714},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12416070699691772},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11070266366004944},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C502989409","wikidata":"https://www.wikidata.org/wiki/Q11425","display_name":"Animation","level":2,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tcad.2019.2907879","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2019.2907879","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:arXiv.org:1903.11264","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1903.11264","pdf_url":"https://arxiv.org/pdf/1903.11264","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"mag:2925003042","is_oa":true,"landing_page_url":"http://arxiv.org/pdf/1903.11264.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"arXiv (Cornell University)","raw_type":null},{"id":"doi:10.48550/arxiv.1903.11264","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.1903.11264","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":"article"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:1903.11264","is_oa":true,"landing_page_url":"http://arxiv.org/abs/1903.11264","pdf_url":"https://arxiv.org/pdf/1903.11264","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5099999904632568,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1639379236","https://openalex.org/W1986225845","https://openalex.org/W2000472712","https://openalex.org/W2036760864","https://openalex.org/W2115819560","https://openalex.org/W2134930324","https://openalex.org/W2140572315","https://openalex.org/W2156341695","https://openalex.org/W2483602548","https://openalex.org/W2588662210","https://openalex.org/W2744873813","https://openalex.org/W2787221846","https://openalex.org/W4242975025"],"related_works":["https://openalex.org/W2738939723","https://openalex.org/W2139605059","https://openalex.org/W2547729116","https://openalex.org/W2794586214","https://openalex.org/W3132061045","https://openalex.org/W3180306599","https://openalex.org/W3052994008","https://openalex.org/W2992038292","https://openalex.org/W2907620743","https://openalex.org/W2911853790","https://openalex.org/W3045379299","https://openalex.org/W1556439630","https://openalex.org/W2546825940","https://openalex.org/W2543815285","https://openalex.org/W2787497939","https://openalex.org/W2970386869","https://openalex.org/W2781862673","https://openalex.org/W2767603112","https://openalex.org/W1914943432","https://openalex.org/W2779162209"],"abstract_inverted_index":{"In":[0,29,109],"this":[1],"paper,":[2],"a":[3],"new":[4],"look-up":[5],"table":[6],"(LUT)":[7],"method":[8],"is":[9,41,96,119],"proposed":[10,31,91,124],"to":[11,71],"reduce":[12],"the":[13,17,30,34,57,66,79,90,93,102,114,123],"simulation":[14,80,87,94],"time":[15,19,59,116],"and":[16,25],"run":[18,58,115],"memory":[20,60,117],"requirement":[21,118],"for":[22,33,107],"large":[23],"logic":[24],"mixed":[26],"signal":[27],"simulations.":[28],"method,":[32,92],"first":[35],"time,":[36],"circuit":[37,48],"with":[38],"multiple":[39],"devices":[40],"replaced":[42],"by":[43,98,122],"one":[44],"LUT":[45,104],"model,":[46],"called":[47],"LUT.":[49],"The":[50,62],"replacement":[51,63],"results":[52,82],"in":[53,83,113],"significant":[54,84],"reduction":[55,85,112],"of":[56,68,86],"requirement.":[61],"also":[64,120],"reduces":[65],"number":[67],"interpolation":[69],"steps":[70],"be":[72],"performed":[73],"at":[74],"every":[75],"Newton-Raphson":[76],"iteration":[77],"during":[78],"that":[81],"time.":[88],"With":[89],"speed":[95],"improved":[97],"two":[99],"times":[100],"over":[101],"conventional":[103],"models":[105],"developed":[106],"devices.":[108],"addition,":[110],"25%":[111],"achieved":[121],"method.":[125]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2022-07-29T00:00:00"}