{"id":"https://openalex.org/W2883160951","doi":"https://doi.org/10.1109/tcad.2018.2878129","title":"Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach","display_name":"Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach","publication_year":2018,"publication_date":"2018-10-25","ids":{"openalex":"https://openalex.org/W2883160951","doi":"https://doi.org/10.1109/tcad.2018.2878129","mag":"2883160951"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2018.2878129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2878129","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071995111","display_name":"Yuzhe Ma","orcid":"https://orcid.org/0000-0002-3612-4182"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Yuzhe Ma","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":"https://orcid.org/0000-0002-3612-4182","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101967869","display_name":"Subhendu Roy","orcid":"https://orcid.org/0000-0001-8554-563X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subhendu Roy","raw_affiliation_strings":["Programmable Solution Group, Intel Corporation, San Jose, USA"],"raw_orcid":"https://orcid.org/0000-0001-8554-563X","affiliations":[{"raw_affiliation_string":"Programmable Solution Group, Intel Corporation, San Jose, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100675222","display_name":"Jin Miao","orcid":"https://orcid.org/0000-0002-0150-4599"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jin Miao","raw_affiliation_strings":["DSG Group, Cadence Design Systems, San Jose, USA"],"raw_orcid":"https://orcid.org/0000-0002-0150-4599","affiliations":[{"raw_affiliation_string":"DSG Group, Cadence Design Systems, San Jose, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087575089","display_name":"Jiamin Chen","orcid":"https://orcid.org/0000-0002-8391-4734"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Jiamin Chen","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":"https://orcid.org/0000-0002-8391-4734","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051340429","display_name":"Bei Yu","orcid":"https://orcid.org/0000-0001-6406-4810"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Bei Yu","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":"https://orcid.org/0000-0001-6406-4810","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.02,"has_fulltext":false,"cited_by_count":49,"citation_normalized_percentile":{"value":0.87375175,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"38","issue":"12","first_page":"2298","last_page":"2311"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11948","display_name":"Machine Learning in Materials Science","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/2505","display_name":"Materials Chemistry"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.813461184501648},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6872121095657349},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.6747705936431885},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5155630111694336},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4510835111141205},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43850529193878174},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.43430477380752563},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3922806978225708},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.35581183433532715},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.32839250564575195},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.22071489691734314},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.19176125526428223},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.17410728335380554},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16762173175811768},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1271125078201294}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.813461184501648},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6872121095657349},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.6747705936431885},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5155630111694336},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4510835111141205},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43850529193878174},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.43430477380752563},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3922806978225708},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.35581183433532715},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.32839250564575195},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.22071489691734314},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.19176125526428223},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.17410728335380554},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16762173175811768},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1271125078201294},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2018.2878129","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2878129","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-120422","is_oa":false,"landing_page_url":"http://www.scopus.com/record/display.url?eid=2-s2.0-85055711331&origin=inward","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1564638059","https://openalex.org/W1746819321","https://openalex.org/W1963965124","https://openalex.org/W1979306010","https://openalex.org/W1997582549","https://openalex.org/W2036402231","https://openalex.org/W2054115349","https://openalex.org/W2061485512","https://openalex.org/W2070410525","https://openalex.org/W2083951140","https://openalex.org/W2101234009","https://openalex.org/W2106089733","https://openalex.org/W2121318693","https://openalex.org/W2131647018","https://openalex.org/W2138209363","https://openalex.org/W2140854523","https://openalex.org/W2141984024","https://openalex.org/W2143785942","https://openalex.org/W2145180784","https://openalex.org/W2147847555","https://openalex.org/W2163199256","https://openalex.org/W2165698076","https://openalex.org/W2167099589","https://openalex.org/W2168543008","https://openalex.org/W2168848751","https://openalex.org/W2242269234","https://openalex.org/W2293147384","https://openalex.org/W2330850558","https://openalex.org/W2339218248","https://openalex.org/W2345438070","https://openalex.org/W2540581201","https://openalex.org/W2744606792","https://openalex.org/W2951665052","https://openalex.org/W3124229194","https://openalex.org/W4211049957","https://openalex.org/W4235507382","https://openalex.org/W4255283007","https://openalex.org/W6675354045","https://openalex.org/W6681338486","https://openalex.org/W6683722355","https://openalex.org/W6764988152"],"related_works":["https://openalex.org/W2171793444","https://openalex.org/W3173072440","https://openalex.org/W2743305891","https://openalex.org/W4387251174","https://openalex.org/W2161355881","https://openalex.org/W2051886008","https://openalex.org/W4235818534","https://openalex.org/W3000171651","https://openalex.org/W4223903705","https://openalex.org/W1975701649"],"abstract_inverted_index":{"In":[0,59],"spite":[1],"of":[2,54,82,98,120,150,163],"maturity":[3],"to":[4,70,93,133],"the":[5,52,95,99,117,122,135,172],"modern":[6],"electronic":[7],"design":[8,24,27,87,169],"automation":[9],"(EDA)":[10],"tools,":[11],"optimized":[12],"designs":[13],"at":[14,185],"architectural":[15,78,114,175],"stage":[16],"may":[17],"become":[18],"suboptimal":[19],"after":[20],"going":[21],"through":[22],"physical":[23,102,177],"flow.":[25],"Adder":[26],"has":[28],"been":[29],"such":[30],"a":[31,64,72,84,167],"long":[32],"studied":[33],"fundamental":[34],"problem":[35],"in":[36,77,101],"very":[37],"large-scale":[38],"integration":[39],"industry":[40],"yet":[41],"designers":[42],"cannot":[43],"achieve":[44,160],"optimal":[45],"solutions":[46],"by":[47,107],"running":[48,109],"EDA":[49,110],"tools":[50,111],"on":[51],"set":[53],"available":[55,184],"prefix":[56,66],"adder":[57,67],"architectures.":[58],"this":[60],"paper,":[61],"we":[62],"enhance":[63],"state-of-the-art":[65],"synthesis":[68],"algorithm":[69,130],"obtain":[71],"much":[73],"wider":[74],"solution":[75],"space":[76,88],"domain.":[79],"On":[80],"top":[81],"that,":[83],"machine":[85],"learning-based":[86],"exploration":[89],"methodology":[90],"is":[91,105,131],"applied":[92],"predict":[94],"Pareto":[96,151,161],"frontier":[97,162],"adders":[100],"domain,":[103],"which":[104,141],"infeasible":[106],"exhaustively":[108],"for":[112,125],"innumerable":[113],"solutions.":[115],"Considering":[116],"high":[118,164],"cost":[119],"obtaining":[121],"true":[123],"values":[124],"learning,":[126],"an":[127],"active":[128],"learning":[129,139],"proposed":[132],"select":[134],"representative":[136],"data":[137,145,182],"during":[138],"process,":[140],"uses":[142],"less":[143],"labeled":[144],"while":[146],"achieving":[147],"better":[148],"quality":[149,165],"frontier.":[152],"Experimental":[153],"results":[154],"demonstrate":[155],"that":[156],"our":[157],"framework":[158],"can":[159],"over":[166],"wide":[168],"space,":[170],"bridging":[171],"gap":[173],"between":[174],"and":[176,181],"designs.":[178],"Source":[179],"code":[180],"are":[183],"<uri":[186],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[187],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">https://github.com/yuzhe630/adder-DSE</uri>":[188],".":[189]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":12},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":10},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
