{"id":"https://openalex.org/W2897282114","doi":"https://doi.org/10.1109/tcad.2018.2877017","title":"A New Paradigm for FPGA Placement Without Explicit Packing","display_name":"A New Paradigm for FPGA Placement Without Explicit Packing","publication_year":2018,"publication_date":"2018-10-19","ids":{"openalex":"https://openalex.org/W2897282114","doi":"https://doi.org/10.1109/tcad.2018.2877017","mag":"2897282114"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2018.2877017","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2877017","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034982668","display_name":"Wuxi Li","orcid":"https://orcid.org/0000-0002-9887-5109"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wuxi Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-9887-5109","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-5705-2501","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5034982668"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":1.178,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.8046114,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":"38","issue":"11","first_page":"2113","last_page":"2126"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8687523007392883},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7658981680870056},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.692184329032898},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6022729277610779},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5748822093009949},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.43295055627822876},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35712140798568726},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33498090505599976},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07198122143745422}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8687523007392883},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7658981680870056},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.692184329032898},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6022729277610779},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5748822093009949},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.43295055627822876},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35712140798568726},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33498090505599976},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07198122143745422},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2018.2877017","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2877017","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1554948125","https://openalex.org/W1986026297","https://openalex.org/W2002641171","https://openalex.org/W2021149030","https://openalex.org/W2029031086","https://openalex.org/W2043679008","https://openalex.org/W2055251702","https://openalex.org/W2057469119","https://openalex.org/W2068115726","https://openalex.org/W2111756578","https://openalex.org/W2120129706","https://openalex.org/W2124537194","https://openalex.org/W2137454730","https://openalex.org/W2139637699","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2163961680","https://openalex.org/W2167190617","https://openalex.org/W2170616854","https://openalex.org/W2328615082","https://openalex.org/W2535860792","https://openalex.org/W2595334824","https://openalex.org/W2626482350","https://openalex.org/W2738078952","https://openalex.org/W2770762651","https://openalex.org/W2771551340","https://openalex.org/W2774510317","https://openalex.org/W2801898382","https://openalex.org/W2886092906","https://openalex.org/W4235234911","https://openalex.org/W4236282544","https://openalex.org/W4245688993","https://openalex.org/W6661169969","https://openalex.org/W6680692090","https://openalex.org/W6753913536"],"related_works":["https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2374017528","https://openalex.org/W4285503609","https://openalex.org/W2126248441","https://openalex.org/W1967938402","https://openalex.org/W2014165129","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248"],"abstract_inverted_index":{"Placement":[0],"and":[1,29,69,77,85],"packing":[2,21,58,70],"are":[3,71],"two":[4],"important":[5],"but":[6],"separated":[7],"optimization":[8],"steps":[9],"in":[10,43,74],"a":[11,36,49,75],"conventional":[12],"field":[13],"programmable":[14],"gate":[15],"array":[16],"(FPGA)":[17],"implementation":[18],"flow.":[19],"A":[20],"engine":[22,38],"clusters":[23],"logic":[24,33],"elements,":[25],"like":[26],"lookup":[27],"tables":[28],"flip-flops,":[30],"into":[31],"configurable":[32],"blocks,":[34],"while":[35],"placement":[37,54,68],"determines":[39],"their":[40],"physical":[41],"locations":[42],"FPGA":[44,53],"layouts.":[45],"This":[46],"paper":[47],"presents":[48],"new":[50],"paradigm":[51],"for":[52],"without":[55],"an":[56],"explicit":[57],"stage.":[59],"In":[60],"the":[61,64,90,93],"proposed":[62,94],"framework,":[63],"solution":[65],"spaces":[66],"of":[67,92],"simultaneously":[72],"explored":[73],"smooth":[76],"elegant":[78],"way.":[79],"Our":[80],"experiments":[81],"on":[82],"ISPD":[83],"2016":[84],"2017":[86],"benchmark":[87],"suites":[88],"demonstrate":[89],"effectiveness":[91],"framework.":[95]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}