{"id":"https://openalex.org/W2883433640","doi":"https://doi.org/10.1109/tcad.2018.2859400","title":"A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization","display_name":"A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization","publication_year":2018,"publication_date":"2018-07-25","ids":{"openalex":"https://openalex.org/W2883433640","doi":"https://doi.org/10.1109/tcad.2018.2859400","mag":"2883433640"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2018.2859400","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2859400","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100768454","display_name":"Kai Huang","orcid":"https://orcid.org/0009-0007-5772-7912"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Kai Huang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100327757","display_name":"Xiaomeng Zhang","orcid":"https://orcid.org/0000-0002-2593-2969"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaomeng Zhang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-2593-2969","affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100705790","display_name":"Dandan Zheng","orcid":"https://orcid.org/0000-0001-6674-2750"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dandan Zheng","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007223576","display_name":"Min Yu","orcid":"https://orcid.org/0000-0002-0538-7297"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Min Yu","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021783986","display_name":"Xiaowen Jiang","orcid":"https://orcid.org/0000-0002-6283-2262"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaowen Jiang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102248428","display_name":"Xiaolang Yan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaolang Yan","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085318038","display_name":"Lisane Brisolara","orcid":"https://orcid.org/0000-0003-3552-4456"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Lisane B. de Brisolara","raw_affiliation_strings":["Technology Development Center, Federal University of Pelotas, Pelotas, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113780350","display_name":"Ahmed Jerraya","orcid":null},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I3020098449","display_name":"CEA Grenoble","ror":"https://ror.org/02mg6n827","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I3020098449"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Ahmed Amine Jerraya","raw_affiliation_strings":["CEA LETI, MINATEC, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CEA LETI, MINATEC, Grenoble, France","institution_ids":["https://openalex.org/I4210150049","https://openalex.org/I899635006","https://openalex.org/I106785703","https://openalex.org/I3020098449","https://openalex.org/I2738703131"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5100768454"],"corresponding_institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":1.5633,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.8507132,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"38","issue":"9","first_page":"1744","last_page":"1757"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7733868956565857},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.6893186569213867},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6688810586929321},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.6392208933830261},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5583316683769226},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5052610039710999},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.44877469539642334},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4271523952484131},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42429015040397644},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.42109936475753784},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4188104271888733},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1636541485786438},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10101374983787537},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0843166708946228}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7733868956565857},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.6893186569213867},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6688810586929321},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.6392208933830261},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5583316683769226},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5052610039710999},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44877469539642334},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4271523952484131},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42429015040397644},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.42109936475753784},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4188104271888733},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1636541485786438},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10101374983787537},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0843166708946228},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2018.2859400","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2859400","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W125936143","https://openalex.org/W1552425406","https://openalex.org/W1561610472","https://openalex.org/W1922576887","https://openalex.org/W1993550521","https://openalex.org/W1994834602","https://openalex.org/W1997723274","https://openalex.org/W2026662237","https://openalex.org/W2034919502","https://openalex.org/W2045929616","https://openalex.org/W2054738230","https://openalex.org/W2055791821","https://openalex.org/W2056303926","https://openalex.org/W2061453292","https://openalex.org/W2064682240","https://openalex.org/W2065713519","https://openalex.org/W2072596277","https://openalex.org/W2081166696","https://openalex.org/W2081818093","https://openalex.org/W2083056378","https://openalex.org/W2090066236","https://openalex.org/W2090930452","https://openalex.org/W2097577132","https://openalex.org/W2097746659","https://openalex.org/W2114577378","https://openalex.org/W2124200646","https://openalex.org/W2126105956","https://openalex.org/W2128637218","https://openalex.org/W2133741166","https://openalex.org/W2140386741","https://openalex.org/W2142386205","https://openalex.org/W2154635391","https://openalex.org/W2166921037","https://openalex.org/W2201299402","https://openalex.org/W2344488400","https://openalex.org/W2514885068","https://openalex.org/W2523248371","https://openalex.org/W2534652523","https://openalex.org/W2558719560","https://openalex.org/W3123757493","https://openalex.org/W3146120420","https://openalex.org/W4250661686","https://openalex.org/W6640279716","https://openalex.org/W6676494795","https://openalex.org/W6678498509","https://openalex.org/W6789420404"],"related_works":["https://openalex.org/W2348165886","https://openalex.org/W1862215007","https://openalex.org/W2003657881","https://openalex.org/W4251719177","https://openalex.org/W4255025037","https://openalex.org/W1989340575","https://openalex.org/W4281711577","https://openalex.org/W2178653557","https://openalex.org/W2106200299","https://openalex.org/W2994908368"],"abstract_inverted_index":{"Task":[0],"mapping":[1,16,46,57,76,84,149],"has":[2],"been":[3,25],"a":[4,156],"hot":[5],"topic":[6],"in":[7],"multiprocessor":[8],"system-on-chip":[9],"software":[10],"design":[11],"for":[12,74,150],"decades.":[13],"During":[14],"the":[15,34,45,89,92,96,103,106,110,117,121,126,129,133,142,147,166,169],"process,":[17,47],"load":[18],"balance":[19],"(LB)":[20],"and":[21,40,48,63,109,114,162],"communication":[22,41,64],"optimization":[23,29],"have":[24],"two":[26],"important":[27],"performance":[28],"factors.":[30],"This":[31],"paper":[32],"studies":[33],"relations":[35],"between":[36],"LB,":[37],"interprocessor":[38],"communications,":[39],"pipeline":[42],"technique":[43],"during":[44],"proposes":[49],"an":[50,70],"integer":[51],"linear":[52],"programming":[53],"(ILP)-based":[54],"static":[55],"task":[56,75,94,107,131],"approach,":[58],"which":[59],"considers":[60],"both":[61,160],"LB":[62],"optimization.":[65],"The":[66],"approach":[67],"consists":[68],"of":[69,91,105,112,128,159,168],"optimized":[71],"ILP":[72,83,93,122,130,143],"model":[73],"with":[77,141],"fewer":[78],"variables":[79],"compared":[80],"to":[81,87,101,145],"previous":[82],"works.":[85],"Moreover,":[86],"enhance":[88],"scalability":[90],"mapping,":[95,132],"task-processor-cluster":[97],"algorithm":[98],"is":[99,138],"proposed":[100,170],"reduce":[102],"scale":[104],"graph":[108],"number":[111],"processors":[113],"then":[115],"solve":[116],"coarse-grained":[118],"input":[119],"by":[120],"mapping.":[123],"To":[124],"increase":[125],"adaptability":[127],"improved":[134],"augmented":[135],"E-constraint":[136],"method":[137],"further":[139],"integrated":[140],"formulations":[144],"select":[146],"best":[148],"different":[151],"applications.":[152],"Experimental":[153],"results":[154],"on":[155],"2/4/8/16/24-CPU":[157],"platform":[158],"synthetic":[161],"real-life":[163],"benchmarks":[164],"demonstrate":[165],"efficiency":[167],"approach.":[171]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
