{"id":"https://openalex.org/W2808295878","doi":"https://doi.org/10.1109/tcad.2018.2846631","title":"Automatic Retiming of Two-Phase Latch-Based Resilient Circuits","display_name":"Automatic Retiming of Two-Phase Latch-Based Resilient Circuits","publication_year":2018,"publication_date":"2018-06-12","ids":{"openalex":"https://openalex.org/W2808295878","doi":"https://doi.org/10.1109/tcad.2018.2846631","mag":"2808295878"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2018.2846631","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2846631","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061179075","display_name":"Huimei Cheng","orcid":"https://orcid.org/0000-0003-1762-7208"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Huimei Cheng","raw_affiliation_strings":["Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-1762-7208","affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080506562","display_name":"Hsiao-Lun Wang","orcid":"https://orcid.org/0000-0003-0493-8701"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hsiao-Lun Wang","raw_affiliation_strings":["Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101470076","display_name":"Minghe Zhang","orcid":"https://orcid.org/0000-0002-5673-3807"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Minghe Zhang","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081079321","display_name":"Dylan Hand","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dylan Hand","raw_affiliation_strings":["Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084205024","display_name":"Peter A. Beerel","orcid":"https://orcid.org/0000-0002-8283-0168"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter A. Beerel","raw_affiliation_strings":["Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-8283-0168","affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5061179075"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":0.6544,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.70957652,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"38","issue":"7","first_page":"1305","last_page":"1316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9945915937423706},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7353200912475586},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7113412022590637},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.558262288570404},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.46462851762771606},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4148101806640625},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.367381751537323},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3518528342247009},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3419678211212158},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2443481981754303},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12418314814567566},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07385513186454773}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9945915937423706},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7353200912475586},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7113412022590637},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.558262288570404},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.46462851762771606},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4148101806640625},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.367381751537323},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3518528342247009},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3419678211212158},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2443481981754303},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12418314814567566},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07385513186454773},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2018.2846631","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2846631","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G105496209","display_name":null,"funder_award_id":"1619415","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1546526482","https://openalex.org/W1911029421","https://openalex.org/W1971700309","https://openalex.org/W1977545325","https://openalex.org/W1998525920","https://openalex.org/W2023185533","https://openalex.org/W2025340565","https://openalex.org/W2082597509","https://openalex.org/W2112759671","https://openalex.org/W2114967122","https://openalex.org/W2124429975","https://openalex.org/W2153495753","https://openalex.org/W2156667996","https://openalex.org/W2157398460","https://openalex.org/W2171577385","https://openalex.org/W2178304595","https://openalex.org/W2215665513","https://openalex.org/W2401797601","https://openalex.org/W2626091927","https://openalex.org/W2751468074","https://openalex.org/W3117862400","https://openalex.org/W3144939025","https://openalex.org/W4213060235","https://openalex.org/W4254147461","https://openalex.org/W4256665635","https://openalex.org/W4285719527","https://openalex.org/W6640006728","https://openalex.org/W6655320552","https://openalex.org/W6672372597","https://openalex.org/W6682231086"],"related_works":["https://openalex.org/W4248668797","https://openalex.org/W4250455229","https://openalex.org/W2111485030","https://openalex.org/W2062802485","https://openalex.org/W2169017341","https://openalex.org/W2126468650","https://openalex.org/W2155487883","https://openalex.org/W1984491986","https://openalex.org/W3143422391","https://openalex.org/W3144756665"],"abstract_inverted_index":{"Timing":[0],"resilient":[1,25,55],"design":[2],"has":[3],"shown":[4],"significant":[5],"promise":[6],"in":[7,52],"mitigating":[8],"the":[9,50,67,84,105,126],"excess":[10],"margins":[11],"associated":[12],"with":[13],"rare":[14],"worst-case":[15],"data":[16],"and":[17,21,40,87,124],"increased":[18],"process,":[19],"voltage,":[20],"temperature":[22],"variations.":[23],"However,":[24],"circuits":[26],"need":[27],"error":[28],"detecting":[29],"sequential":[30],"logic":[31],"(EDL)":[32],"to":[33,48,65,77,82,97,135,139],"detect":[34],"timing":[35],"errors":[36],"which":[37,103],"incur":[38],"area":[39,90,129],"power":[41],"overhead.":[42],"This":[43],"paper":[44],"proposes":[45],"two":[46],"alternatives":[47],"reduce":[49,125],"overhead":[51,86],"two-phase":[53],"latch-based":[54],"circuits.":[56],"The":[57,70],"first":[58],"is":[59],"a":[60,73,98,109],"new":[61],"resiliency-aware":[62],"graph-based":[63],"approach":[64],"solve":[66],"retiming":[68,101],"problem.":[69],"second":[71],"uses":[72],"virtual":[74],"resynthesis":[75],"library":[76],"enable":[78],"commercial":[79],"synthesis":[80],"tools":[81],"recognize":[83],"EDL":[85],"optimize":[88],"total":[89,127],"during":[91],"retiming.":[92,141],"We":[93],"compare":[94],"both":[95],"approaches":[96],"commercially":[99],"standard":[100],"approach,":[102],"ignores":[104],"resiliency":[106],"overheads,":[107],"on":[108],"wide":[110],"variety":[111],"of":[112,133],"benchmarks.":[113],"Our":[114],"experimental":[115],"results":[116],"show":[117],"that":[118],"our":[119],"methods":[120],"are":[121],"computationally":[122],"efficient":[123],"circuit":[128],"by":[130],"an":[131],"average":[132],"up":[134],"10%-15%":[136],"when":[137],"compared":[138],"traditional":[140]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
