{"id":"https://openalex.org/W2792821003","doi":"https://doi.org/10.1109/tcad.2018.2802871","title":"SWIFT: Switch-Level Fault Simulation on GPUs","display_name":"SWIFT: Switch-Level Fault Simulation on GPUs","publication_year":2018,"publication_date":"2018-02-05","ids":{"openalex":"https://openalex.org/W2792821003","doi":"https://doi.org/10.1109/tcad.2018.2802871","mag":"2792821003"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2018.2802871","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2802871","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101864125","display_name":"Eric Schneider","orcid":"https://orcid.org/0000-0003-2296-1956"},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Eric Schneider","raw_affiliation_strings":["Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany"],"raw_orcid":"https://orcid.org/0000-0003-2296-1956","affiliations":[{"raw_affiliation_string":"Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008775226","display_name":"Hans-Joachim Wunderlich","orcid":"https://orcid.org/0000-0003-4536-8290"},"institutions":[{"id":"https://openalex.org/I100066346","display_name":"University of Stuttgart","ror":"https://ror.org/04vnq7t77","country_code":"DE","type":"education","lineage":["https://openalex.org/I100066346"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Hans-Joachim Wunderlich","raw_affiliation_strings":["Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany"],"raw_orcid":"https://orcid.org/0000-0003-4536-8290","affiliations":[{"raw_affiliation_string":"Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, Germany","institution_ids":["https://openalex.org/I100066346"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I100066346"],"apc_list":null,"apc_paid":null,"fwci":1.1891,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81352187,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"38","issue":"1","first_page":"122","last_page":"135"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7314721941947937},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6327943801879883},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.5996653437614441},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4966936707496643},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4906257688999176},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.45450761914253235},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.44963595271110535},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44285815954208374},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.4354790151119232},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42979976534843445},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.428165465593338},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.42301851511001587},{"id":"https://openalex.org/keywords/fault-simulator","display_name":"Fault Simulator","score":0.4221719205379486},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4155277609825134},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3853796422481537},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3786226511001587},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.3690716624259949},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22665253281593323},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.2224108874797821},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1324406862258911},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10288101434707642},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10009995102882385},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08283686637878418}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7314721941947937},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6327943801879883},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.5996653437614441},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4966936707496643},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4906257688999176},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.45450761914253235},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.44963595271110535},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44285815954208374},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.4354790151119232},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42979976534843445},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.428165465593338},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.42301851511001587},{"id":"https://openalex.org/C2776365744","wikidata":"https://www.wikidata.org/wiki/Q5438149","display_name":"Fault Simulator","level":5,"score":0.4221719205379486},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4155277609825134},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3853796422481537},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3786226511001587},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.3690716624259949},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22665253281593323},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.2224108874797821},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1324406862258911},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10288101434707642},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10009995102882385},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08283686637878418},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2018.2802871","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2018.2802871","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G428805383","display_name":null,"funder_award_id":"WU 245/17-1","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"},{"id":"https://openalex.org/G4537181528","display_name":null,"funder_award_id":"WU 245/16-1","funder_id":"https://openalex.org/F4320320879","funder_display_name":"Deutsche Forschungsgemeinschaft"}],"funders":[{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":59,"referenced_works":["https://openalex.org/W612784192","https://openalex.org/W1489242265","https://openalex.org/W1508076293","https://openalex.org/W1637395447","https://openalex.org/W1919670594","https://openalex.org/W1969903927","https://openalex.org/W1975338463","https://openalex.org/W1980942247","https://openalex.org/W1981663184","https://openalex.org/W1984485372","https://openalex.org/W1996109429","https://openalex.org/W2008990681","https://openalex.org/W2046817879","https://openalex.org/W2047821116","https://openalex.org/W2048597497","https://openalex.org/W2059454390","https://openalex.org/W2061946964","https://openalex.org/W2062716389","https://openalex.org/W2069345435","https://openalex.org/W2069802878","https://openalex.org/W2070617947","https://openalex.org/W2070888360","https://openalex.org/W2074088078","https://openalex.org/W2097579272","https://openalex.org/W2100636574","https://openalex.org/W2109524145","https://openalex.org/W2115296652","https://openalex.org/W2120116751","https://openalex.org/W2125169487","https://openalex.org/W2129437137","https://openalex.org/W2133250872","https://openalex.org/W2134895826","https://openalex.org/W2140194001","https://openalex.org/W2146685901","https://openalex.org/W2154695555","https://openalex.org/W2156443301","https://openalex.org/W2160547280","https://openalex.org/W2167078995","https://openalex.org/W2169375167","https://openalex.org/W2277653173","https://openalex.org/W2294988400","https://openalex.org/W2295862081","https://openalex.org/W2345447838","https://openalex.org/W2401610261","https://openalex.org/W2492599081","https://openalex.org/W2511040012","https://openalex.org/W2548602630","https://openalex.org/W2564408197","https://openalex.org/W2566658637","https://openalex.org/W2793366120","https://openalex.org/W3141440412","https://openalex.org/W3147150317","https://openalex.org/W3149604617","https://openalex.org/W4235485521","https://openalex.org/W4237090517","https://openalex.org/W4250981202","https://openalex.org/W4253495214","https://openalex.org/W4254506919","https://openalex.org/W6749921928"],"related_works":["https://openalex.org/W2031110496","https://openalex.org/W2157154381","https://openalex.org/W2149684986","https://openalex.org/W3147038789","https://openalex.org/W4253743993","https://openalex.org/W2542800311","https://openalex.org/W2288548055","https://openalex.org/W2913077774","https://openalex.org/W1923485359","https://openalex.org/W4248287414"],"abstract_inverted_index":{"Current":[0],"nanometer":[1],"CMOS":[2,42],"circuits":[3],"show":[4],"an":[5],"increasing":[6],"sensitivity":[7],"to":[8,36,71,94,105],"deviations":[9],"in":[10,121,185],"first-order":[11],"parameters":[12,91],"and":[13,23,47,98,111,123,128,159,177,189],"suffer":[14],"from":[15,155],"process":[16,48],"variations":[17,49],"during":[18],"manufacturing.":[19],"To":[20],"properly":[21],"assess":[22],"support":[24],"test":[25],"validation":[26],"of":[27,41,101,115,132,167,175,187],"digital":[28],"designs,":[29],"low-level":[30,59],"fault":[31,82,180],"simulation":[32,60,83,143,181],"approaches":[33,61],"are":[34,92],"utilized":[35,93],"accurately":[37],"capture":[38,95],"the":[39,55,113,139,163,168],"behavior":[40,100],"cells":[43,103,122],"under":[44],"parametric":[45],"faults":[46,107,133],"as":[50,52],"early":[51],"possible":[53],"throughout":[54],"design":[56],"phase.":[57],"However,":[58],"exhibit":[62],"a":[63,79],"high":[64],"computational":[65],"complexity,":[66],"especially":[67],"when":[68],"variation":[69,119,130],"has":[70],"be":[72],"taken":[73],"into":[74],"account.":[75],"In":[76],"this":[77],"paper,":[78],"high-throughput":[80],"parallel":[81],"at":[84,182],"switch":[85],"level":[86,184],"is":[87],"presented.":[88],"First-order":[89],"electrical":[90],"CMOS-specific":[96],"functional":[97],"timing":[99],"complex":[102],"allowing":[104],"model":[106],"with":[108,173],"transistor":[109,124],"granularity":[110],"without":[112],"need":[114],"logic":[116,183],"abstraction.":[117],"Furthermore,":[118],"modeling":[120],"devices":[125],"enables":[126],"broad":[127],"efficient":[129],"analyses":[131],"over":[134],"many":[135],"circuit":[136,160],"instances":[137],"for":[138],"first":[140],"time.":[141],"The":[142],"approach":[144],"utilizes":[145],"massive":[146],"parallelization":[147],"on":[148],"graphics":[149],"processing":[150],"units":[151],"by":[152],"exploiting":[153],"parallelism":[154],"cells,":[156],"stimuli,":[157],"faults,":[158],"instances.":[161],"Despite":[162],"lower":[164],"abstraction":[165],"levels":[166],"approach,":[169],"it":[170],"processes":[171],"designs":[172],"millions":[174],"gates":[176],"outperforms":[178],"conventional":[179],"terms":[186],"speed":[188],"accuracy.":[190]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-08-14T07:06:38.338062","created_date":"2025-10-10T00:00:00"}