{"id":"https://openalex.org/W2770762651","doi":"https://doi.org/10.1109/tcad.2017.2778058","title":"RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs","display_name":"RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs","publication_year":2017,"publication_date":"2017-11-28","ids":{"openalex":"https://openalex.org/W2770762651","doi":"https://doi.org/10.1109/tcad.2017.2778058","mag":"2770762651"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2017.2778058","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2778058","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052177721","display_name":"Gengjie Chen","orcid":"https://orcid.org/0000-0001-6016-4742"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Gengjie Chen","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080499552","display_name":"Chak-Wa Pui","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Chak-Wa Pui","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063427343","display_name":"Wing-Kai Chow","orcid":"https://orcid.org/0000-0002-0433-3078"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Wing-Kai Chow","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067085786","display_name":"Ka-Chun Lam","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Ka-Chun Lam","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062061242","display_name":"Jian Kuang","orcid":"https://orcid.org/0000-0002-2659-0040"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Jian Kuang","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Evangeline F. Y. Young","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051340429","display_name":"Bei Yu","orcid":"https://orcid.org/0000-0001-6406-4810"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Bei Yu","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":1.9713,"has_fulltext":false,"cited_by_count":56,"citation_normalized_percentile":{"value":0.87539237,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"37","issue":"10","first_page":"2022","last_page":"2035"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8431100845336914},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7323307991027832},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6869326829910278},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5851203799247742},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5106561779975891},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.390765517950058}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8431100845336914},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7323307991027832},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6869326829910278},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5851203799247742},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5106561779975891},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.390765517950058}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2017.2778058","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2778058","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7978088210","display_name":null,"funder_award_id":"CUHK14206015","funder_id":"https://openalex.org/F4320321592","funder_display_name":"Research Grants Council, University Grants Committee"}],"funders":[{"id":"https://openalex.org/F4320321592","display_name":"Research Grants Council, University Grants Committee","ror":"https://ror.org/00djwmt25"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":73,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1554948125","https://openalex.org/W1575153928","https://openalex.org/W1605203071","https://openalex.org/W1922167881","https://openalex.org/W1963908543","https://openalex.org/W1966460368","https://openalex.org/W1984283136","https://openalex.org/W1991576731","https://openalex.org/W2002641171","https://openalex.org/W2003145440","https://openalex.org/W2005602803","https://openalex.org/W2014070364","https://openalex.org/W2018721259","https://openalex.org/W2020549672","https://openalex.org/W2023428606","https://openalex.org/W2023788229","https://openalex.org/W2029031086","https://openalex.org/W2029459574","https://openalex.org/W2029462965","https://openalex.org/W2037266728","https://openalex.org/W2055251702","https://openalex.org/W2065295938","https://openalex.org/W2067856828","https://openalex.org/W2075137913","https://openalex.org/W2078174680","https://openalex.org/W2079559808","https://openalex.org/W2083637347","https://openalex.org/W2090317622","https://openalex.org/W2109220922","https://openalex.org/W2111104699","https://openalex.org/W2111756578","https://openalex.org/W2120129706","https://openalex.org/W2120970098","https://openalex.org/W2124537194","https://openalex.org/W2131920591","https://openalex.org/W2132450497","https://openalex.org/W2132693178","https://openalex.org/W2137454730","https://openalex.org/W2138206217","https://openalex.org/W2139637699","https://openalex.org/W2147542748","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2154014710","https://openalex.org/W2154302973","https://openalex.org/W2158961316","https://openalex.org/W2162141797","https://openalex.org/W2163608025","https://openalex.org/W2166747627","https://openalex.org/W2328615082","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2538165366","https://openalex.org/W2584883722","https://openalex.org/W2738078952","https://openalex.org/W3141147179","https://openalex.org/W3145128584","https://openalex.org/W4234143391","https://openalex.org/W4246219036","https://openalex.org/W6628664065","https://openalex.org/W6641576374","https://openalex.org/W6656321663","https://openalex.org/W6657560448","https://openalex.org/W6667947448","https://openalex.org/W6676486451","https://openalex.org/W6676627073","https://openalex.org/W6676886990","https://openalex.org/W6680484343","https://openalex.org/W6680692090","https://openalex.org/W6684188114","https://openalex.org/W6732945326","https://openalex.org/W6733018185"],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2984236338","https://openalex.org/W3146360095","https://openalex.org/W2096844293","https://openalex.org/W2018147837","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2184011203","https://openalex.org/W2570254841"],"abstract_inverted_index":{"As":[0],"a":[1,62,89],"good":[2],"tradeoff":[3],"between":[4],"central":[5],"processing":[6],"unit":[7],"(CPU)":[8],"and":[9,27,32,45,58,79,92,133],"application":[10],"specific":[11],"integrated":[12],"circuit":[13],"(ASIC),":[14],"field-programmable":[15],"gate":[16],"array":[17],"(FPGA)":[18],"is":[19,97],"becoming":[20],"more":[21],"widely":[22],"used":[23],"in":[24],"both":[25],"industry":[26],"academia.":[28],"The":[29],"increasing":[30],"complexity":[31],"scale":[33],"of":[34,64,105],"modern":[35],"FPGA,":[36],"however,":[37],"impose":[38],"great":[39],"challenges":[40],"on":[41],"the":[42,56,87,103,118,139],"FPGA":[43,141],"placement":[44,59,83],"packing":[46,57,73],"problem.":[47],"In":[48],"this":[49],"paper,":[50],"we":[51],"propose":[52],"RippleFPGA":[53,127],"to":[54,75,102,116,137],"solve":[55],"simultaneously":[60],"through":[61],"set":[63],"novel":[65],"techniques:":[66],"1)":[67],"smooth":[68],"stair-step":[69],"flow;":[70],"2)":[71],"implicit":[72],"similar":[74],"ASIC":[76],"legalization":[77],"(LG);":[78],"3)":[80],"two-level":[81],"detailed":[82],"(DP).":[84],"To":[85],"enable":[86],"flow,":[88],"generic,":[90],"efficient,":[91],"false-alarm-free":[93],"legality":[94],"checking":[95],"method":[96],"also":[98],"proposed.":[99],"Besides,":[100],"due":[101],"insufficiency":[104],"ASIC-like":[106],"congestion":[107],"alleviation":[108],"methods,":[109],"some":[110],"FPGA-routing-architecture-aware":[111],"optimization":[112],"techniques":[113],"are":[114],"proposed":[115],"improve":[117],"routability.":[119],"When":[120],"evaluated":[121],"by":[122],"ISPD":[123],"2016":[124],"Contest":[125],"benchmarks,":[126],"has":[128],"5.1%":[129],"better":[130],"routed":[131],"wirelength":[132],"5.5\u00d7":[134],"speedup":[135],"compared":[136],"all":[138],"state-of-the-art":[140],"placers.":[142]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":3}],"updated_date":"2026-07-13T07:31:44.756512","created_date":"2025-10-10T00:00:00"}
