{"id":"https://openalex.org/W2762644533","doi":"https://doi.org/10.1109/tcad.2017.2762921","title":"DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance","display_name":"DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance","publication_year":2017,"publication_date":"2017-10-13","ids":{"openalex":"https://openalex.org/W2762644533","doi":"https://doi.org/10.1109/tcad.2017.2762921","mag":"2762644533"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2017.2762921","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2762921","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083056788","display_name":"Ishan Thakkar","orcid":"https://orcid.org/0000-0002-7289-1530"},"institutions":[{"id":"https://openalex.org/I92446798","display_name":"Colorado State University","ror":"https://ror.org/03k1gpj17","country_code":"US","type":"education","lineage":["https://openalex.org/I92446798"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ishan G. Thakkar","raw_affiliation_strings":["Department Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Department Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I92446798"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018382547","display_name":"Sudeep Pasricha","orcid":"https://orcid.org/0000-0002-0846-0066"},"institutions":[{"id":"https://openalex.org/I92446798","display_name":"Colorado State University","ror":"https://ror.org/03k1gpj17","country_code":"US","type":"education","lineage":["https://openalex.org/I92446798"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudeep Pasricha","raw_affiliation_strings":["Department Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA"],"affiliations":[{"raw_affiliation_string":"Department Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA","institution_ids":["https://openalex.org/I92446798"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083056788"],"corresponding_institution_ids":["https://openalex.org/I92446798"],"apc_list":null,"apc_paid":null,"fwci":2.4785,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.90939398,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"37","issue":"9","first_page":"1760","last_page":"1773"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7889304161071777},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6484174132347107},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5584596395492554},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5034937262535095},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.5027370452880859},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4639567732810974},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4450654685497284},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.44393211603164673},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4390980303287506},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3898797333240509},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3618735671043396},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.3550630807876587},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.35109376907348633},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2043282687664032},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08120596408843994},{"id":"https://openalex.org/keywords/phase-change","display_name":"Phase change","score":0.08119413256645203}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7889304161071777},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6484174132347107},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5584596395492554},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5034937262535095},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.5027370452880859},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4639567732810974},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4450654685497284},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.44393211603164673},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4390980303287506},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3898797333240509},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3618735671043396},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.3550630807876587},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.35109376907348633},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2043282687664032},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08120596408843994},{"id":"https://openalex.org/C133256868","wikidata":"https://www.wikidata.org/wiki/Q7180940","display_name":"Phase change","level":2,"score":0.08119413256645203},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C61696701","wikidata":"https://www.wikidata.org/wiki/Q770766","display_name":"Engineering physics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2017.2762921","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2762921","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1375667714","display_name":null,"funder_award_id":"FA9550-13-1-0110","funder_id":"https://openalex.org/F4320338279","funder_display_name":"Air Force Office of Scientific Research"}],"funders":[{"id":"https://openalex.org/F4320338279","display_name":"Air Force Office of Scientific Research","ror":"https://ror.org/011e9bt93"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":47,"referenced_works":["https://openalex.org/W1483176180","https://openalex.org/W1520257495","https://openalex.org/W1983826793","https://openalex.org/W1984381469","https://openalex.org/W1985263063","https://openalex.org/W1986418066","https://openalex.org/W1996160696","https://openalex.org/W2000270805","https://openalex.org/W2010202670","https://openalex.org/W2018497748","https://openalex.org/W2019701892","https://openalex.org/W2032818550","https://openalex.org/W2035575158","https://openalex.org/W2036934942","https://openalex.org/W2041588416","https://openalex.org/W2048588974","https://openalex.org/W2055818721","https://openalex.org/W2077770351","https://openalex.org/W2082070657","https://openalex.org/W2089101985","https://openalex.org/W2097823832","https://openalex.org/W2102449048","https://openalex.org/W2112753327","https://openalex.org/W2121795083","https://openalex.org/W2124165274","https://openalex.org/W2138436606","https://openalex.org/W2141527188","https://openalex.org/W2147657366","https://openalex.org/W2157587823","https://openalex.org/W2159862818","https://openalex.org/W2169863928","https://openalex.org/W2169875292","https://openalex.org/W2204664557","https://openalex.org/W2212068638","https://openalex.org/W2212947641","https://openalex.org/W2293209826","https://openalex.org/W2315876256","https://openalex.org/W2404547066","https://openalex.org/W2528917738","https://openalex.org/W2539921360","https://openalex.org/W3145572630","https://openalex.org/W4246750084","https://openalex.org/W4253877280","https://openalex.org/W6658639229","https://openalex.org/W6659185519","https://openalex.org/W6671183045","https://openalex.org/W6792931021"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2019238062","https://openalex.org/W2185658074","https://openalex.org/W4285245242","https://openalex.org/W3049130895","https://openalex.org/W4243618206","https://openalex.org/W2138825797","https://openalex.org/W2896161911","https://openalex.org/W119142178","https://openalex.org/W1455439291"],"abstract_inverted_index":{"A":[0],"major":[1],"challenge":[2],"for":[3,21],"the":[4,24,41,56,67,86,127,134,142,149,153],"widespread":[5],"adoption":[6],"of":[7,26,43,60,85,105,144,152,214],"phase":[8],"change":[9],"memory":[10,14,159,181,189,204,206,231],"(PCM)":[11],"as":[12],"main":[13],"is":[15,36,64],"its":[16,163],"asymmetric":[17],"write":[18,58,95,99,150],"latency.":[19],"Generally,":[20],"a":[22,27,44,61,74,92,112,171],"PCM,":[23],"latency":[25,42,59],"SET":[28,69,88],"operation":[29,32,46,49],"(i.e.,":[30,47],"an":[31,48],"that":[33,50,125,177,196,233],"writes":[34,51],"\u201c1\u201d)":[35],"2-5":[37],"times":[38],"longer":[39],"than":[40],"RESET":[45],"\u201c0\u201d).":[52],"For":[53],"this":[54,115,167],"reason,":[55],"average":[57,226],"PCM":[62,76,124,235],"system":[63],"limited":[65],"by":[66,169],"high-latency":[68],"operations.":[70],"This":[71],"paper":[72],"presents":[73],"novel":[75,119],"architecture":[77],"called":[78],"DyPhase,":[79],"which":[80,155],"uses":[81],"partial-SET":[82,106],"operations":[83,89,122,147],"instead":[84],"conventional":[87],"to":[90,114,131],"introduce":[91],"symmetry":[93],"in":[94,123,156,184],"latency,":[96],"thereby":[97],"increasing":[98],"performance":[100,139],"and":[101,161,187,221],"throughput.":[102],"However,":[103],"use":[104,143],"decreases":[107,162],"data":[108,136],"retention":[109],"time.":[110],"As":[111],"remedy":[113],"problem,":[116],"DyPhase":[117,165,198],"employs":[118],"distributed":[120],"refresh":[121,146],"leverage":[126],"available":[128],"power":[129],"budget":[130],"periodically":[132,178],"rewrite":[133],"stored":[135],"with":[137,192,210],"minimal":[138],"overhead.":[140],"Unfortunately,":[141],"periodic":[145],"increases":[148],"rate":[151],"memory,":[154],"turn":[157],"accelerates":[158],"degradation":[160,186],"lifetime.":[164,190],"overcomes":[166],"shortcoming":[168],"utilizing":[170],"proactive":[172],"in-situ":[173],"self-annealing":[174],"(PISA)":[175],"technique":[176],"heals":[179],"degraded":[180],"cells,":[182],"resulting":[183],"decelerated":[185],"increased":[188],"Experiments":[191],"PARSEC":[193],"benchmarks":[194],"indicate":[195],"our":[197],"architecture-based":[199],"hybrid":[200,229],"dynamic":[201],"random":[202],"access":[203],"(DRAM)-PCM":[205],"system,":[207],"when":[208],"enabled":[209],"PISA,":[211],"yields":[212],"orders":[213],"magnitude":[215],"higher":[216],"lifetime,":[217],"8.3%":[218],"less":[219,223],"CPI,":[220],"44.3%":[222],"EDP":[224],"on":[225],"over":[227],"other":[228],"DRAM-PCM":[230],"systems":[232],"utilize":[234],"architectures":[236],"from":[237],"prior":[238],"works.":[239]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}