{"id":"https://openalex.org/W2738393560","doi":"https://doi.org/10.1109/tcad.2017.2731679","title":"Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes","display_name":"Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes","publication_year":2017,"publication_date":"2017-07-24","ids":{"openalex":"https://openalex.org/W2738393560","doi":"https://doi.org/10.1109/tcad.2017.2731679","mag":"2738393560"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2017.2731679","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2731679","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073582440","display_name":"Sorin Dobre","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sorin Adrian Dobre","raw_affiliation_strings":["Qualcomm Technologies, Inc., San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"Qualcomm Technologies, Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["University of California at San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California at San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100454287","display_name":"Jiajia Li","orcid":"https://orcid.org/0000-0002-3420-9764"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California, San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiajia Li","raw_affiliation_strings":["University of California at San Diego, La Jolla, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California at San Diego, La Jolla, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073582440"],"corresponding_institution_ids":["https://openalex.org/I4210087596"],"apc_list":null,"apc_paid":null,"fwci":0.5734,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.69312879,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"37","issue":"4","first_page":"855","last_page":"868"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8539245128631592},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6208910346031189},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5967755913734436},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5281096696853638},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5249576568603516},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.5035709738731384},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5025415420532227},{"id":"https://openalex.org/keywords/network-planning-and-design","display_name":"Network planning and design","score":0.4617040753364563},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4449284076690674},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4391607642173767},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.42963385581970215},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.42515045404434204},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.4121132791042328},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.33893004059791565},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.32270270586013794},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.28960728645324707},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2010212242603302},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1913478970527649},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18766289949417114},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.16817554831504822},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16557297110557556},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16240093111991882},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.13898658752441406}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8539245128631592},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6208910346031189},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5967755913734436},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5281096696853638},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5249576568603516},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.5035709738731384},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5025415420532227},{"id":"https://openalex.org/C114563136","wikidata":"https://www.wikidata.org/wiki/Q19725982","display_name":"Network planning and design","level":2,"score":0.4617040753364563},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4449284076690674},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4391607642173767},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.42963385581970215},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.42515045404434204},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4121132791042328},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.33893004059791565},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.32270270586013794},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.28960728645324707},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2010212242603302},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1913478970527649},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18766289949417114},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.16817554831504822},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16557297110557556},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16240093111991882},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.13898658752441406},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C147789679","wikidata":"https://www.wikidata.org/wiki/Q11372","display_name":"Physical chemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2017.2731679","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2731679","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7099999785423279,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1967800299","https://openalex.org/W1977774784","https://openalex.org/W1982199193","https://openalex.org/W2077021817","https://openalex.org/W2109184897","https://openalex.org/W2110721922","https://openalex.org/W2115256077","https://openalex.org/W2116319078","https://openalex.org/W2128174223","https://openalex.org/W2146554181","https://openalex.org/W2166295488","https://openalex.org/W2168048050","https://openalex.org/W2168908650","https://openalex.org/W2248512261","https://openalex.org/W2535234615","https://openalex.org/W4238153486","https://openalex.org/W4238906052","https://openalex.org/W4252332481","https://openalex.org/W6676809168","https://openalex.org/W6681767608","https://openalex.org/W6684740691","https://openalex.org/W6684805869"],"related_works":["https://openalex.org/W2781601456","https://openalex.org/W3010631755","https://openalex.org/W2186482337","https://openalex.org/W2151657833","https://openalex.org/W2070693700","https://openalex.org/W1488283129","https://openalex.org/W2156138647","https://openalex.org/W2365114398","https://openalex.org/W1617216077","https://openalex.org/W1987597317"],"abstract_inverted_index":{"Standard-cell":[0],"libraries":[1],"can":[2],"be":[3],"developed":[4],"with":[5,42,79,91,117,141,168,229],"different":[6,15,80,180],"cell":[7,20,101,143,164,199],"heights":[8,21,44,81,92,121,144,165,181],"(e.g.,":[9,182],"in":[10,48,109,113,122,145],"FinFET":[11],"technology,":[12],"corresponding":[13],"to":[14,59,76,137,205,223],"numbers":[16],"of":[17,30,96,163,171,176,179,188,193],"fins).":[18],"Larger":[19],"provide":[22],"higher":[23],"drive":[24,53],"strengths,":[25],"but":[26,50],"at":[27,82],"the":[28,83,110,152,160,172,183,218],"cost":[29],"larger":[31],"area":[32,186,208,232],"and":[33,55,64,71,159,174,196,209,221,231],"power":[34,210,230],"consumption":[35],"as":[36,38],"well":[37],"pin":[39,65],"capacitance.":[40],"Cells":[41],"smaller":[43,47],"are":[45,56,74],"relatively":[46],"area,":[49],"have":[51],"weaker":[52],"strengths":[54],"more":[57],"likely":[58],"suffer":[60],"from":[61],"routing":[62],"congestion":[63],"accessibility":[66],"issues.":[67],"Existing":[68],"design":[69,107,134,139],"methodologies":[70],"tool":[72],"flows":[73],"able":[75],"mix":[77],"cells":[78,90,116,178],"block":[84,88],"level":[85],"(i.e.,":[86],"each":[87],"contains":[89],"being":[93],"integer":[94],"multiples":[95],"a":[97,123,131,146],"particular":[98],"\u201csingle":[99],"row\u201d":[100],"height).":[102],"To":[103],"our":[104,201],"knowledge,":[105],"no":[106],"methodology":[108],"literature":[111],"or":[112],"production":[114],"mixes":[115],"different,":[118],"noninteger":[119],"multiple":[120],"fine-grained":[124,147],"manner.":[125,148],"In":[126],"this":[127],"paper,":[128],"we":[129],"propose":[130],"novel":[132],"physical":[133],"optimization":[135,150,202],"flow":[136],"implement":[138],"blocks":[140],"mixed":[142],"Our":[149],"resolves":[151],"\u201cchicken-and-egg\u201d":[153],"loop":[154],"between":[155,191],"floorplan":[156],"site":[157],"definition":[158],"optimized":[161],"choices":[162],"after":[166],"placement":[167],"full":[169],"comprehension":[170],"constraints":[173],"costs":[175],"mixing":[177],"\u201cbreaker":[184],"cell\u201d":[185],"overheads":[187],"row":[189],"alignment":[190],"sub-blocks":[192],"8":[194,235],"T":[195,198],"12":[197,213],"rows),":[200],"achieves":[203],"up":[204,222],"over":[206,224],"30%":[207],"reductions":[211,233],"versus":[212,234],"T-only":[214,236],"implementation":[215],"while":[216],"maintaining":[217],"same":[219],"performance,":[220],"10%":[225],"performance":[226],"improvement":[227],"along":[228],"implementation.":[237]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}