{"id":"https://openalex.org/W2738078952","doi":"https://doi.org/10.1109/tcad.2017.2729349","title":"UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing","display_name":"UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing","publication_year":2017,"publication_date":"2017-07-19","ids":{"openalex":"https://openalex.org/W2738078952","doi":"https://doi.org/10.1109/tcad.2017.2729349","mag":"2738078952"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2017.2729349","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2729349","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034982668","display_name":"Wuxi Li","orcid":"https://orcid.org/0000-0002-9887-5109"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Wuxi Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-9887-5109","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015818630","display_name":"Shounak Dhar","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shounak Dhar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-5705-2501","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5034982668"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":4.0911,"has_fulltext":false,"cited_by_count":77,"citation_normalized_percentile":{"value":0.94424669,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"37","issue":"4","first_page":"869","last_page":"882"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.849890947341919},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8027569055557251},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6904863119125366},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5563096404075623},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45437097549438477},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4381580352783203},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.13478848338127136}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.849890947341919},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8027569055557251},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6904863119125366},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5563096404075623},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45437097549438477},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4381580352783203},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.13478848338127136},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2017.2729349","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2729349","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1575153928","https://openalex.org/W1583136220","https://openalex.org/W1963908543","https://openalex.org/W1977545325","https://openalex.org/W1978383095","https://openalex.org/W1986026297","https://openalex.org/W2002641171","https://openalex.org/W2020549672","https://openalex.org/W2021149030","https://openalex.org/W2029031086","https://openalex.org/W2055251702","https://openalex.org/W2057469119","https://openalex.org/W2075137913","https://openalex.org/W2079559808","https://openalex.org/W2106448546","https://openalex.org/W2111756578","https://openalex.org/W2113267287","https://openalex.org/W2119354760","https://openalex.org/W2124537194","https://openalex.org/W2135606070","https://openalex.org/W2137454730","https://openalex.org/W2138206217","https://openalex.org/W2139637699","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2154014710","https://openalex.org/W2154302973","https://openalex.org/W2158961316","https://openalex.org/W2162141797","https://openalex.org/W2165419774","https://openalex.org/W2167190617","https://openalex.org/W2533722497","https://openalex.org/W2535860792","https://openalex.org/W2538165366","https://openalex.org/W3141147179","https://openalex.org/W4213060235","https://openalex.org/W4236282544","https://openalex.org/W4249211602","https://openalex.org/W6680484343"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W2745001401","https://openalex.org/W4321353415","https://openalex.org/W2130974462","https://openalex.org/W972276598","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W2082487009"],"abstract_inverted_index":{"Field":[0],"programmable":[1],"gate":[2],"array":[3],"(FPGA)":[4],"packing":[5,21,42,60],"and":[6,22,43,52,57,62,78,107],"placement":[7,23,44,66,100],"without":[8],"routability":[9],"consideration":[10],"could":[11],"lead":[12],"to":[13,27,31],"unroutable":[14],"results":[15],"for":[16],"high-utilization":[17],"designs.":[18],"Conventional":[19],"FPGA":[20,41,73,99],"approaches":[24],"are":[25,68],"shown":[26],"have":[28],"severe":[29],"difficulties":[30],"yield":[32],"good":[33],"routability.":[34,53],"In":[35],"this":[36],"paper,":[37],"we":[38],"propose":[39],"an":[40],"engine":[45],"called":[46],"UTPlaceF":[47,70,102],"that":[48],"simultaneously":[49,75],"optimizes":[50],"wirelength":[51,111],"A":[54],"novel":[55],"physical":[56],"congestion":[58],"aware":[59],"algorithm":[61],"a":[63],"hierarchical":[64],"detailed":[65],"technique":[67],"proposed.":[69],"outperforms":[71],"state-of-the-art":[72],"placers":[74],"in":[76],"runtime":[77],"solution":[79],"quality":[80],"on":[81,84],"International":[82],"Symposium":[83],"Physical":[85],"Design":[86],"(ISPD)":[87],"2016":[88],"benchmark":[89],"suite.":[90],"Compared":[91],"with":[92,112],"the":[93],"top":[94],"three":[95],"winners":[96],"of":[97],"ISPD'16":[98],"contest,":[101],"can":[103],"deliver":[104],"6.2%,":[105],"11.6%,":[106],"29.1%":[108],"better":[109],"routed":[110],"shorter":[113],"runtime.":[114]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":11},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":7},{"year":2019,"cited_by_count":11},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
