{"id":"https://openalex.org/W2569250791","doi":"https://doi.org/10.1109/tcad.2017.2648839","title":"Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs","display_name":"Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs","publication_year":2017,"publication_date":"2017-01-05","ids":{"openalex":"https://openalex.org/W2569250791","doi":"https://doi.org/10.1109/tcad.2017.2648839","mag":"2569250791"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2017.2648839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2648839","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055630366","display_name":"Shreepad Panth","orcid":"https://orcid.org/0000-0001-6296-8453"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shreepad Panth","raw_affiliation_strings":["Intel Corporation, San Jose, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-6296-8453","affiliations":[{"raw_affiliation_string":"Intel Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025604916","display_name":"Kambiz Samadi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kambiz Samadi","raw_affiliation_strings":["Qualcomm Technologies Inc., San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm Technologies Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058197553","display_name":"Yang Du","orcid":"https://orcid.org/0000-0003-2254-778X"},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yang Du","raw_affiliation_strings":["Qualcomm Technologies Inc., San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm Technologies Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.2241,"has_fulltext":false,"cited_by_count":90,"citation_normalized_percentile":{"value":0.9461222,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"36","issue":"10","first_page":"1716","last_page":"1724"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8898870944976807},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6479787826538086},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6212355494499207},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5695861577987671},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.5684651732444763},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5563284754753113},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5121824741363525},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.5068944096565247},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45712512731552124},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.419717401266098},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3899235129356384},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3400491178035736},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3107389211654663},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22018063068389893},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.11515522003173828},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07673493027687073}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8898870944976807},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6479787826538086},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6212355494499207},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5695861577987671},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.5684651732444763},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5563284754753113},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5121824741363525},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.5068944096565247},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45712512731552124},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.419717401266098},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3899235129356384},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3400491178035736},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3107389211654663},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22018063068389893},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.11515522003173828},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07673493027687073},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2017.2648839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2017.2648839","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320308258","display_name":"Qualcomm","ror":"https://ror.org/002zrf773"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1963985775","https://openalex.org/W1993632150","https://openalex.org/W2013397418","https://openalex.org/W2128998437","https://openalex.org/W2157629140","https://openalex.org/W2163262984","https://openalex.org/W2170052777","https://openalex.org/W2245094412","https://openalex.org/W4246766117"],"related_works":["https://openalex.org/W2350308400","https://openalex.org/W1995821058","https://openalex.org/W2157541699","https://openalex.org/W3129822007","https://openalex.org/W146048418","https://openalex.org/W2115502122","https://openalex.org/W4386859294","https://openalex.org/W2148021977","https://openalex.org/W2138401961","https://openalex.org/W2967850598"],"abstract_inverted_index":{"Monolithic":[0],"3-D":[1,18,43,65],"(M3D)":[2],"integrated":[3],"circuits":[4],"(ICs)":[5],"are":[6],"an":[7,33,46],"emerging":[8],"technology":[9],"that":[10,92],"offer":[11],"much":[12],"higher":[13],"integration":[14],"densities":[15],"than":[16],"previous":[17],"IC":[19],"approaches.":[20],"In":[21],"this":[22],"paper,":[23],"we":[24,93],"present":[25],"a":[26,75,81,104],"complete":[27],"netlist-to-layout":[28],"design":[29,32,50],"flow":[30,51],"to":[31,39,97],"M3D":[34,47],"block,":[35],"as":[36,38,74],"well":[37],"integrate":[40],"2-D":[41,59,114],"and":[42,61,90,99,107],"blocks":[44],"into":[45],"SoC.":[48],"This":[49],"is":[52],"based":[53],"on":[54,86],"commercial":[55,118],"tools":[56],"built":[57],"for":[58,103],"ICs,":[60],"enhanced":[62],"with":[63,112],"our":[64],"specific":[66],"methodologies.":[67],"We":[68],"use":[69],"the":[70],"OpenSPARC":[71],"T2":[72],"SoC":[73],"case":[76],"study,":[77],"implement":[78],"it":[79],"in":[80],"28-nm":[82],"fully":[83],"depleted":[84],"silicon":[85],"insulator":[87],"foundry":[88],"process,":[89],"demonstrate":[91],"can":[94],"achieve":[95],"up":[96],"12%":[98],"8%":[100],"power":[101],"savings":[102],"single":[105],"block":[106],"SoC,":[108],"respectively,":[109],"when":[110],"compared":[111],"their":[113],"counterparts":[115],"implemented":[116],"using":[117],"tools.":[119]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":16},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":14},{"year":2020,"cited_by_count":10},{"year":2019,"cited_by_count":15},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
