{"id":"https://openalex.org/W2141988600","doi":"https://doi.org/10.1109/tcad.2015.2440316","title":"Robust Optimization of Multiple Timing Constraints","display_name":"Robust Optimization of Multiple Timing Constraints","publication_year":2015,"publication_date":"2015-06-02","ids":{"openalex":"https://openalex.org/W2141988600","doi":"https://doi.org/10.1109/tcad.2015.2440316","mag":"2141988600"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2015.2440316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2015.2440316","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078217124","display_name":"Michael Wainberg","orcid":"https://orcid.org/0000-0001-6061-0239"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Michael Wainberg","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","Department of Electrical & Computer Engineering, University of Toronto, Toronto, On, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","Department of Electrical & Computer Engineering, University of Toronto, Toronto, On, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5078217124"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":0.5919,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.72563528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"34","issue":"12","first_page":"1942","last_page":"1953"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.8099812269210815},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6932622790336609},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6774266958236694},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.632239818572998},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5261352062225342},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.47146087884902954},{"id":"https://openalex.org/keywords/extension","display_name":"Extension (predicate logic)","score":0.4646686017513275},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.46104806661605835},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4351716637611389},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41149604320526123},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3763151168823242},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.34721845388412476},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27965959906578064},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24892717599868774},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.125345379114151},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08210793137550354}],"concepts":[{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.8099812269210815},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6932622790336609},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6774266958236694},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.632239818572998},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5261352062225342},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.47146087884902954},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.4646686017513275},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.46104806661605835},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4351716637611389},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41149604320526123},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3763151168823242},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.34721845388412476},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27965959906578064},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24892717599868774},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.125345379114151},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08210793137550354},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2015.2440316","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2015.2440316","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320307801","display_name":"Texas Instruments","ror":"https://ror.org/03vsmv677"},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1964360685","https://openalex.org/W1964784760","https://openalex.org/W1977505713","https://openalex.org/W2005602803","https://openalex.org/W2023428606","https://openalex.org/W2079559808","https://openalex.org/W2084083833","https://openalex.org/W2094806828","https://openalex.org/W2100502052","https://openalex.org/W2111756578","https://openalex.org/W2115047803","https://openalex.org/W2121244114","https://openalex.org/W2135606070","https://openalex.org/W2138383740","https://openalex.org/W2154014710","https://openalex.org/W2157406114","https://openalex.org/W2159221249","https://openalex.org/W2164340799","https://openalex.org/W2179314520","https://openalex.org/W2275304190","https://openalex.org/W2409361203","https://openalex.org/W2409595827","https://openalex.org/W2496543017","https://openalex.org/W4238008789","https://openalex.org/W4238070904"],"related_works":["https://openalex.org/W2144282137","https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W2127379989","https://openalex.org/W2136196184","https://openalex.org/W2087612346","https://openalex.org/W1514283284","https://openalex.org/W2144518356","https://openalex.org/W2075400577","https://openalex.org/W2121694082"],"abstract_inverted_index":{"Modern":[0],"field-programmable":[1],"gate":[2],"array":[3],"(FPGA)":[4],"circuit":[5],"designs":[6],"often":[7],"contain":[8],"multiple":[9,53,82,101,119],"clocks":[10],"and":[11,15,110,131],"complex":[12],"timing":[13,20,48,54,96,102],"constraints,":[14,103],"achieving":[16],"these":[17],"constraints":[18,55,83,120,128,140],"requires":[19],"optimization":[21,62,97],"at":[22],"all":[23],"stages":[24],"of":[25,84,95,145],"the":[26,106,124],"computer-aided":[27],"design":[28],"(CAD)":[29],"flow.":[30],"To":[31],"our":[32],"knowledge,":[33],"no":[34],"prior":[35],"published":[36],"work":[37],"has":[38],"either":[39],"described":[40],"or":[41,87],"quantitatively":[42],"evaluated":[43],"how":[44],"to":[45,58,71],"compute":[46],"connection":[47],"criticalities":[49],"for":[50,79,98],"circuits":[51,80,99],"with":[52,81,100,138],"in":[56,105,123],"order":[57],"best":[59],"guide":[60],"CAD":[61,113],"algorithms.":[63],"While":[64],"single-clock":[65,146],"techniques":[66],"have":[67],"a":[68,92,142],"simple":[69],"extension":[70,144],"multi-clock":[72],"circuits,":[73],"this":[74],"formulation":[75,116],"is":[76],"not":[77],"robust":[78,93],"different":[85],"magnitudes,":[86],"impossible":[88],"constraints.":[89],"We":[90],"describe":[91],"method":[94],"implemented":[104],"open-source":[107],"versatile":[108],"place":[109],"route":[111],"FPGA":[112],"tool.":[114],"Our":[115],"can":[117],"optimize":[118],"well,":[121],"even":[122],"case":[125],"where":[126],"some":[127],"are":[129],"impossible,":[130],"achieves":[132],"over":[133],"20%":[134],"greater":[135],"clock":[136],"speed":[137],"aggressive":[139],"than":[141],"straight-forward":[143],"work.":[147]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
