{"id":"https://openalex.org/W2016461982","doi":"https://doi.org/10.1109/tcad.2013.2293539","title":"Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure","display_name":"Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure","publication_year":2014,"publication_date":"2014-03-17","ids":{"openalex":"https://openalex.org/W2016461982","doi":"https://doi.org/10.1109/tcad.2013.2293539","mag":"2016461982"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2013.2293539","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2293539","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026975930","display_name":"Xiang Qiu","orcid":null},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiang Qiu","raw_affiliation_strings":["University of California, Santa Barbara, CA, USA","University of California Santa Barbara Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"University of California Santa Barbara Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063371595","display_name":"Malgorzata Marek-Sadowska","orcid":"https://orcid.org/0000-0002-3934-7031"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malgorzata Marek-Sadowska","raw_affiliation_strings":["University of California, Santa Barbara, CA, USA","University of California Santa Barbara Santa Barbara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]},{"raw_affiliation_string":"University of California Santa Barbara Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013238154","display_name":"W. Maly","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wojciech P. Maly","raw_affiliation_strings":["Carnegie Mellon University, Pittsburg, PA, USA","Carnegie Mellon University, Pittsburg, PA USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburg, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon University, Pittsburg, PA USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4503,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.84008052,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"33","issue":"4","first_page":"495","last_page":"506"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8722351789474487},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.594342052936554},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5279920101165771},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5221831798553467},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4926946461200714},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.49054521322250366},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47418293356895447},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44210201501846313},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.415221631526947},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4045085906982422},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3601030707359314},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.334292471408844},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0709916353225708},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06461796164512634}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8722351789474487},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.594342052936554},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5279920101165771},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5221831798553467},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4926946461200714},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.49054521322250366},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47418293356895447},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44210201501846313},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.415221631526947},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4045085906982422},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3601030707359314},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.334292471408844},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0709916353225708},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06461796164512634},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2013.2293539","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2293539","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1671229861","https://openalex.org/W1971233263","https://openalex.org/W1984791779","https://openalex.org/W1987067207","https://openalex.org/W2010747748","https://openalex.org/W2026543046","https://openalex.org/W2070686838","https://openalex.org/W2105616993","https://openalex.org/W2112813001","https://openalex.org/W2116625560","https://openalex.org/W2121878622","https://openalex.org/W2130871230","https://openalex.org/W2134487287","https://openalex.org/W2137978785","https://openalex.org/W2141803235","https://openalex.org/W2161903232","https://openalex.org/W2161906825","https://openalex.org/W2290590898","https://openalex.org/W2545316175","https://openalex.org/W2560851059","https://openalex.org/W2586794790","https://openalex.org/W4234740743","https://openalex.org/W6676777394","https://openalex.org/W6680745868","https://openalex.org/W6683820115","https://openalex.org/W6696841707","https://openalex.org/W6730472457"],"related_works":["https://openalex.org/W2889102485","https://openalex.org/W2388299947","https://openalex.org/W2134697552","https://openalex.org/W4385831984","https://openalex.org/W3047211184","https://openalex.org/W2158494242","https://openalex.org/W2169589717","https://openalex.org/W4243638536","https://openalex.org/W2183559057","https://openalex.org/W8358306"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"demonstrate":[4,75],"that":[5,35],"standard":[6],"cell":[7],"design":[8,14],"methodology":[9],"can":[10],"be":[11],"applied":[12],"to":[13,44,47,81],"vertical":[15],"slit":[16],"field":[17],"effect":[18],"transistor":[19],"(VeSFET)-based":[20],"ASICs":[21],"with":[22,50,62],"modern":[23],"CMOS":[24,67],"EDA":[25],"tools.":[26],"We":[27,57],"study":[28],"a":[29,63],"family":[30],"of":[31,41,54],"VeSFET":[32,51,71],"canvases-chain":[33],"canvases":[34,52],"improve":[36],"performance":[37],"and":[38,69],"power":[39,66,77],"consumption":[40],"circuits":[42,48],"mapped":[43],"them":[45],"compared":[46,80],"implemented":[49,61],"composed":[53],"isolated":[55],"transistors.":[56],"compare":[58],"the":[59,82,86],"designs":[60,74,84],"commercial":[64],"low":[65],"library":[68],"corresponding":[70],"libraries.":[72],"VeSFET-based":[73],"significant":[76],"reduction":[78],"as":[79],"CMOS-based":[83],"at":[85],"same":[87],"performance.":[88]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}