{"id":"https://openalex.org/W2035652262","doi":"https://doi.org/10.1109/tcad.2013.2292504","title":"Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions","display_name":"Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions","publication_year":2014,"publication_date":"2014-02-13","ids":{"openalex":"https://openalex.org/W2035652262","doi":"https://doi.org/10.1109/tcad.2013.2292504","mag":"2035652262"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2013.2292504","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2292504","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080600205","display_name":"Jian Yao","orcid":"https://orcid.org/0000-0003-2622-0215"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jian Yao","raw_affiliation_strings":["Tsinghua University, Institute of Microelectronics, Beijing, China","Inst. of Microelectron., Tsinghua Univ., Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Institute of Microelectronics, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]},{"raw_affiliation_string":"Inst. of Microelectron., Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112436964","display_name":"Zuochang Ye","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zuochang Ye","raw_affiliation_strings":["Tsinghua University, Institute of Microelectronics, Beijing, China","Inst. of Microelectron., Tsinghua Univ., Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Institute of Microelectronics, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]},{"raw_affiliation_string":"Inst. of Microelectron., Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100617593","display_name":"Yan Wang","orcid":"https://orcid.org/0000-0003-4851-6113"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yan Wang","raw_affiliation_strings":["Tsinghua University, Institute of Microelectronics, Beijing, China","Inst. of Microelectron., Tsinghua Univ., Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tsinghua University, Institute of Microelectronics, Beijing, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"]},{"raw_affiliation_string":"Inst. of Microelectron., Tsinghua Univ., Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.7737,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.90574351,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"33","issue":"3","first_page":"384","last_page":"396"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.6906026601791382},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.6415138244628906},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6311763525009155},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6295097470283508},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5693992972373962},{"id":"https://openalex.org/keywords/boundary","display_name":"Boundary (topology)","score":0.565233588218689},{"id":"https://openalex.org/keywords/importance-sampling","display_name":"Importance sampling","score":0.5358838438987732},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5148979425430298},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.49886488914489746},{"id":"https://openalex.org/keywords/failure-rate","display_name":"Failure rate","score":0.49443578720092773},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45076996088027954},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.42238086462020874},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.21825644373893738},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.21219009160995483},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18735632300376892},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.18621742725372314},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18003079295158386},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.07485803961753845},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.06919103860855103}],"concepts":[{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.6906026601791382},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.6415138244628906},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6311763525009155},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6295097470283508},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5693992972373962},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.565233588218689},{"id":"https://openalex.org/C52740198","wikidata":"https://www.wikidata.org/wiki/Q1539564","display_name":"Importance sampling","level":3,"score":0.5358838438987732},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5148979425430298},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.49886488914489746},{"id":"https://openalex.org/C163164238","wikidata":"https://www.wikidata.org/wiki/Q2737027","display_name":"Failure rate","level":2,"score":0.49443578720092773},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45076996088027954},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.42238086462020874},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.21825644373893738},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.21219009160995483},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18735632300376892},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.18621742725372314},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18003079295158386},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.07485803961753845},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.06919103860855103},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2013.2292504","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2292504","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":42,"referenced_works":["https://openalex.org/W309569989","https://openalex.org/W643521013","https://openalex.org/W659475733","https://openalex.org/W1667165204","https://openalex.org/W1695563742","https://openalex.org/W1973057345","https://openalex.org/W1973615069","https://openalex.org/W1980147245","https://openalex.org/W1996241861","https://openalex.org/W2018044188","https://openalex.org/W2018632396","https://openalex.org/W2033246483","https://openalex.org/W2043419861","https://openalex.org/W2057920591","https://openalex.org/W2059797154","https://openalex.org/W2076884803","https://openalex.org/W2103793078","https://openalex.org/W2118749577","https://openalex.org/W2119312496","https://openalex.org/W2120353978","https://openalex.org/W2121200747","https://openalex.org/W2121429049","https://openalex.org/W2123085386","https://openalex.org/W2143301592","https://openalex.org/W2154962044","https://openalex.org/W2155583994","https://openalex.org/W2162870748","https://openalex.org/W2169189905","https://openalex.org/W3139804307","https://openalex.org/W3149202397","https://openalex.org/W3151457670","https://openalex.org/W4213121121","https://openalex.org/W4243073678","https://openalex.org/W4247460323","https://openalex.org/W4249753629","https://openalex.org/W4252766109","https://openalex.org/W4256012597","https://openalex.org/W4297970750","https://openalex.org/W4300580367","https://openalex.org/W6663221386","https://openalex.org/W6677720047","https://openalex.org/W6678199778"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2096437374","https://openalex.org/W1943174035","https://openalex.org/W1928481607","https://openalex.org/W3135165657","https://openalex.org/W1485582195","https://openalex.org/W57337972","https://openalex.org/W1561306903","https://openalex.org/W2563702065","https://openalex.org/W2119025037"],"abstract_inverted_index":{"SRAM":[0],"cells":[1],"generally":[2],"require":[3],"an":[4],"extremely":[5],"low":[6],"failure":[7,37,81,121],"rate":[8],"(i.e.,":[9],"high":[10],"yield)":[11],"in":[12,70],"the":[13,24,57,98,111],"per":[14],"cell":[15],"basis":[16],"to":[17,35,76,95],"ensure":[18],"a":[19,52],"reasonably":[20],"moderate":[21],"yield":[22,28],"for":[23,116],"whole":[25],"chip.":[26],"Existing":[27],"analysis":[29],"methods":[30],"still":[31],"encounter":[32],"issues":[33,69],"related":[34],"multiple":[36,46,120],"regions":[38,82],"resulting":[39],"from":[40],"high-dimensional":[41],"process":[42],"parameter":[43],"space":[44],"and/or":[45],"performance":[47],"specifications.":[48],"This":[49],"paper":[50],"proposes":[51],"new":[53],"method":[54,99,113],"that":[55,101,110],"combines":[56],"advantages":[58],"of":[59],"existing":[60,133],"importance":[61,86],"sampling":[62,87],"and":[63,67,83],"boundary":[64],"searching":[65],"methods,":[66],"avoids":[68],"both.":[71],"The":[72],"key":[73],"idea":[74],"is":[75,114],"first":[77],"find":[78],"all":[79],"likely":[80],"then,":[84],"do":[85],"on":[88],"these":[89],"regions.":[90,122],"Surrogate":[91],"models":[92],"are":[93],"used":[94],"further":[96],"accelerate":[97],"so":[100],"SPICE-simulations":[102],"can":[103,125],"be":[104],"highly":[105],"reduced.":[106],"Experimental":[107],"results":[108],"show":[109],"proposed":[112],"suitable":[115],"handling":[117],"problems":[118],"with":[119],"Meanwhile,":[123],"it":[124],"provide":[126],"5X":[127],"~":[128],"20X":[129],"speed-up":[130],"over":[131],"other":[132],"techniques.":[134]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}