{"id":"https://openalex.org/W2081719483","doi":"https://doi.org/10.1109/tcad.2013.2284190","title":"Sequential Equivalence Checking for Clock-Gated Circuits","display_name":"Sequential Equivalence Checking for Clock-Gated Circuits","publication_year":2014,"publication_date":"2014-01-24","ids":{"openalex":"https://openalex.org/W2081719483","doi":"https://doi.org/10.1109/tcad.2013.2284190","mag":"2081719483"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2013.2284190","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2284190","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043552025","display_name":"H. Savoj","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hamid Savoj","raw_affiliation_strings":["Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USA","Electr. Eng. & Comput. Sci. Dept., Univ. of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Electr. Eng. & Comput. Sci. Dept., Univ. of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USA","Electr. Eng. & Comput. Sci. Dept., Univ. of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Electr. Eng. & Comput. Sci. Dept., Univ. of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064568178","display_name":"Robert K. Brayton","orcid":"https://orcid.org/0000-0002-3861-1718"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Brayton","raw_affiliation_strings":["Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USA","Electr. Eng. & Comput. Sci. Dept., Univ. of California at Berkeley, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Electr. Eng. & Comput. Sci. Dept., Univ. of California at Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":1.2431,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.82752765,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"33","issue":"2","first_page":"305","last_page":"317"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.8888739347457886},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.7756485939025879},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6711511611938477},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.6285550594329834},{"id":"https://openalex.org/keywords/controllability","display_name":"Controllability","score":0.6154650449752808},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5738762021064758},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.5418769121170044},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5274294018745422},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.49131718277931213},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4649812877178192},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.4384623169898987},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.43763548135757446},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.42617395520210266},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37585368752479553},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3258378505706787},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.293314129114151},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.275127649307251},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.18548715114593506},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1380290389060974},{"id":"https://openalex.org/keywords/applied-mathematics","display_name":"Applied mathematics","score":0.089138925075531}],"concepts":[{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.8888739347457886},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.7756485939025879},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6711511611938477},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.6285550594329834},{"id":"https://openalex.org/C48209547","wikidata":"https://www.wikidata.org/wiki/Q1331104","display_name":"Controllability","level":2,"score":0.6154650449752808},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5738762021064758},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.5418769121170044},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5274294018745422},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.49131718277931213},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4649812877178192},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.4384623169898987},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.43763548135757446},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.42617395520210266},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37585368752479553},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3258378505706787},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.293314129114151},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.275127649307251},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.18548715114593506},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1380290389060974},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.089138925075531},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcad.2013.2284190","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2284190","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.220.9506","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.220.9506","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecs.berkeley.edu/%7Ealanmi/publications/2012/iwls12_cgt.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.642.7826","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.642.7826","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecs.berkeley.edu/~alanmi/publications/2014/tcad14_cg.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1587808985","https://openalex.org/W1967444133","https://openalex.org/W1973665222","https://openalex.org/W2040632328","https://openalex.org/W2046401607","https://openalex.org/W2060407451","https://openalex.org/W2097136089","https://openalex.org/W2099994752","https://openalex.org/W2111982322","https://openalex.org/W2137564865","https://openalex.org/W2163492807","https://openalex.org/W2163921844","https://openalex.org/W3150268867","https://openalex.org/W3151473321","https://openalex.org/W4237084505","https://openalex.org/W4239481074","https://openalex.org/W4249287540","https://openalex.org/W6665802101","https://openalex.org/W6675742074"],"related_works":["https://openalex.org/W2145377621","https://openalex.org/W2160837527","https://openalex.org/W2129192090","https://openalex.org/W4245788159","https://openalex.org/W1989297294","https://openalex.org/W2932636172","https://openalex.org/W4248668797","https://openalex.org/W2111485030","https://openalex.org/W2125651818","https://openalex.org/W4235754909"],"abstract_inverted_index":{"Sequential":[0],"logic":[1],"synthesis":[2],"often":[3],"leads":[4],"to":[5,12,27,95],"substantially":[6],"easier":[7],"equivalence":[8,15,30],"checking":[9,16,31],"problems,":[10],"compared":[11],"general-case":[13],"sequential":[14,43,49],"(SEC).":[17],"This":[18],"paper":[19],"theoretically":[20],"investigates":[21],"when":[22,42],"SEC":[23],"can":[24,39],"be":[25,40],"reduced":[26],"a":[28,81],"combinational":[29],"(CEC)":[32],"problem.":[33],"It":[34],"shows":[35],"how":[36],"the":[37,66,73,77,92],"theory":[38],"applied":[41],"transforms":[44,60],"are":[45],"used,":[46],"such":[47,59],"as":[48],"clock":[50],"gating,":[51],"retiming,":[52],"and":[53,86,98],"redundancy":[54],"removal.":[55],"The":[56],"legitimacy":[57],"of":[58,84],"is":[61,89],"typically":[62],"justified":[63],"intuitively,":[64],"by":[65],"designer":[67],"or":[68],"software":[69],"developer":[70],"believing":[71],"that":[72],"two":[74],"circuits":[75],"reach":[76],"same":[78],"state":[79],"after":[80],"finite":[82],"number":[83],"cycles,":[85],"no":[87],"difference":[88],"observed":[90],"at":[91],"outputs":[93],"due":[94],"fanin":[96],"non-controllability":[97],"fanout":[99],"non-observability":[100],"effects.":[101]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}