{"id":"https://openalex.org/W1996489373","doi":"https://doi.org/10.1109/tcad.2013.2275252","title":"Performance Estimation Techniques With MPSoC Transaction-Accurate Models","display_name":"Performance Estimation Techniques With MPSoC Transaction-Accurate Models","publication_year":2013,"publication_date":"2013-11-19","ids":{"openalex":"https://openalex.org/W1996489373","doi":"https://doi.org/10.1109/tcad.2013.2275252","mag":"1996489373"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2013.2275252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2275252","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101655468","display_name":"De Ma","orcid":"https://orcid.org/0000-0001-8700-938X"},"institutions":[{"id":"https://openalex.org/I1327237609","display_name":"Ministry of Education of the People's Republic of China","ror":"https://ror.org/01mv9t934","country_code":"CN","type":"government","lineage":["https://openalex.org/I1327237609","https://openalex.org/I4210127390"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"De Ma","raw_affiliation_strings":["Ministry of Education, Key Laboratory of RF Circuits and Systems, Hangzhou, China","Key Lab. of RF Circuits & Syst., Zhejiang Univ., Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ministry of Education, Key Laboratory of RF Circuits and Systems, Hangzhou, China","institution_ids":["https://openalex.org/I1327237609"]},{"raw_affiliation_string":"Key Lab. of RF Circuits & Syst., Zhejiang Univ., Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100329480","display_name":"Rongjie Yan","orcid":"https://orcid.org/0000-0001-5225-6268"},"institutions":[{"id":"https://openalex.org/I4210128818","display_name":"Institute of Software","ror":"https://ror.org/033dfsn42","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210128818"]},{"id":"https://openalex.org/I4391767820","display_name":"State Key Laboratory of Computer Science","ror":"https://ror.org/01hsx4r68","country_code":null,"type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210128818","https://openalex.org/I4391767820"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rongjie Yan","raw_affiliation_strings":["Institute of Software, State Key Laboratory of Computer Science, Beijing, China","State Key Lab. of Comput. Sci., Inst. of Software, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Software, State Key Laboratory of Computer Science, Beijing, China","institution_ids":["https://openalex.org/I4210128818","https://openalex.org/I4391767820"]},{"raw_affiliation_string":"State Key Lab. of Comput. Sci., Inst. of Software, Beijing, China","institution_ids":["https://openalex.org/I4210128818"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100768452","display_name":"Kai Huang","orcid":"https://orcid.org/0000-0003-0359-7810"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kai Huang","raw_affiliation_strings":["Zhejiang University, Institute of VLSI Design, Hangzhou, China","Institute of VLSI Design Zhejiang University Hangzhou China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Institute of VLSI Design, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University Hangzhou China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007223576","display_name":"Min Yu","orcid":"https://orcid.org/0000-0002-0538-7297"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Min Yu","raw_affiliation_strings":["Zhejiang University, Institute of VLSI Design, Hangzhou, China","Institute of VLSI Design Zhejiang University Hangzhou China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Institute of VLSI Design, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University Hangzhou China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074059776","display_name":"Siwen Xiu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Siwen Xiu","raw_affiliation_strings":["Zhejiang University, Institute of VLSI Design, Hangzhou, China","Institute of VLSI Design Zhejiang University Hangzhou China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Institute of VLSI Design, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University Hangzhou China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003880973","display_name":"GE Hai-tong","orcid":null},"institutions":[{"id":"https://openalex.org/I4210142178","display_name":"Hangzhou DAC Biotech (China)","ror":"https://ror.org/04hy71c73","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210142178"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haitong Ge","raw_affiliation_strings":["Hangzhou C-Sky Micro-system Company, Hangzhou, China","Hangzhou C-Sky Micro-Syst. Co., Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hangzhou C-Sky Micro-system Company, Hangzhou, China","institution_ids":[]},{"raw_affiliation_string":"Hangzhou C-Sky Micro-Syst. Co., Hangzhou, China","institution_ids":["https://openalex.org/I4210142178"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101586250","display_name":"Xiaolang Yan","orcid":"https://orcid.org/0000-0003-2284-3036"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaolang Yan","raw_affiliation_strings":["Zhejiang University, Institute of VLSI Design, Hangzhou, China","Institute of VLSI Design Zhejiang University Hangzhou China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zhejiang University, Institute of VLSI Design, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]},{"raw_affiliation_string":"Institute of VLSI Design Zhejiang University Hangzhou China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113780350","display_name":"Ahmed Jerraya","orcid":null},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I3020098449","display_name":"CEA Grenoble","ror":"https://ror.org/02mg6n827","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I3020098449"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Ahmed Amine Jerraya","raw_affiliation_strings":["CEA-LETI, MINATEC, Grenoble Cedex, France","LETI, CEA, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CEA-LETI, MINATEC, Grenoble Cedex, France","institution_ids":["https://openalex.org/I4210150049","https://openalex.org/I899635006","https://openalex.org/I106785703","https://openalex.org/I3020098449","https://openalex.org/I2738703131"]},{"raw_affiliation_string":"LETI, CEA, Grenoble, France","institution_ids":["https://openalex.org/I4210150049","https://openalex.org/I3020098449","https://openalex.org/I2738703131"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2202,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.87357906,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"32","issue":"12","first_page":"1920","last_page":"1933"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8795821666717529},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7232974767684937},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7074094414710999},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5210604071617126},{"id":"https://openalex.org/keywords/profiling","display_name":"Profiling (computer programming)","score":0.5192142128944397},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.508991003036499},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.48000043630599976},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4782485067844391},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42664700746536255},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3694832921028137},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3517695665359497},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.34378930926322937},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.2961854934692383},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.2626655697822571},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17309647798538208},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.15379709005355835}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8795821666717529},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7232974767684937},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7074094414710999},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5210604071617126},{"id":"https://openalex.org/C187191949","wikidata":"https://www.wikidata.org/wiki/Q1138496","display_name":"Profiling (computer programming)","level":2,"score":0.5192142128944397},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.508991003036499},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.48000043630599976},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4782485067844391},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42664700746536255},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3694832921028137},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3517695665359497},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.34378930926322937},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2961854934692383},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.2626655697822571},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17309647798538208},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.15379709005355835}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2013.2275252","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2275252","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1970939331","https://openalex.org/W1981268630","https://openalex.org/W1986449043","https://openalex.org/W1995783333","https://openalex.org/W1996142033","https://openalex.org/W2076285066","https://openalex.org/W2088572851","https://openalex.org/W2096258337","https://openalex.org/W2101631461","https://openalex.org/W2114435074","https://openalex.org/W2120452217","https://openalex.org/W2130080799","https://openalex.org/W2131583907","https://openalex.org/W2152857845","https://openalex.org/W2161115325","https://openalex.org/W2170692588","https://openalex.org/W2171997938","https://openalex.org/W2486320888","https://openalex.org/W3137094666","https://openalex.org/W3144830948","https://openalex.org/W3148717140","https://openalex.org/W4251534053"],"related_works":["https://openalex.org/W87257424","https://openalex.org/W2169347615","https://openalex.org/W4388405798","https://openalex.org/W4226457259","https://openalex.org/W4287828549","https://openalex.org/W3010473754","https://openalex.org/W4295235956","https://openalex.org/W1994858553","https://openalex.org/W2119548576","https://openalex.org/W15724499"],"abstract_inverted_index":{"Efficient":[0],"design":[1],"of":[2,32,57,69,137,179,186],"multiprocessor":[3],"system-on-chip":[4],"(MPSoC)":[5],"requires":[6],"early,":[7],"fast,":[8],"and":[9,93,100,111,149],"accurate":[10,28,35,181],"performance":[11,29],"estimation":[12,177],"techniques.":[13],"In":[14,74],"this":[15],"paper,":[16],"we":[17],"present":[18],"new":[19],"techniques":[20,156,173],"based":[21],"on":[22,50,157,195],"fine-grained":[23],"code":[24,71],"analysis":[25],"to":[26,64,81,106,117,131,184],"estimate":[27,83,107],"during":[30],"simulation":[31,47,196],"MPSoC":[33],"transaction":[34,180],"models.":[36],"First,":[37],"a":[38,76,112,192],"GCC":[39],"profiling":[40,52],"tool":[41],"is":[42,62,79,115,129],"applied":[43,154],"in":[44],"the":[45,51,58,66,119,133,187],"native":[46],"process.":[48],"Based":[49],"result,":[53],"an":[54,125,158],"instruction":[55,101],"analyzer":[56,78],"target":[59],"CPU":[60],"architecture":[61],"proposed":[63,105],"analyze":[65],"cycle":[67],"cost":[68,92],"C":[70],"under":[72],"estimation.":[73],"addition,":[75],"memory":[77,84,95,134,142,150],"used":[80],"further":[82],"access":[85,96,127,135,143],"latency":[86,144],"including":[87],"both":[88],"instruction/data":[89],"cache":[90,102,108,120],"time":[91],"global":[94,141],"cycles.":[97],"Both":[98],"data":[99],"models":[103,121,182],"are":[104],"miss":[109],"penalty,":[110],"segment-based":[113],"strategy":[114],"adopted":[116],"update":[118],"more":[122],"efficiently.":[123],"Furthermore,":[124],"equalized":[126],"model":[128],"presented":[130],"imitate":[132],"behavior":[136],"processors":[138],"for":[139],"estimating":[140],"caused":[145],"by":[146],"bus":[147],"contention":[148],"bandwidth.":[151],"We":[152],"have":[153],"these":[155,172],"H.264":[159],"decoder":[160],"application":[161],"with":[162,191],"different":[163],"hardware":[164],"architectures.":[165],"The":[166],"experimental":[167],"results":[168],"show":[169],"that":[170,185],"applying":[171],"can":[174],"obviously":[175],"improve":[176],"accuracy":[178],"close":[183],"virtual":[188],"prototype":[189],"models,":[190],"tolerable":[193],"overhead":[194],"speed.":[197]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
