{"id":"https://openalex.org/W1969546595","doi":"https://doi.org/10.1109/tcad.2013.2269768","title":"An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture","display_name":"An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture","publication_year":2013,"publication_date":"2013-10-16","ids":{"openalex":"https://openalex.org/W1969546595","doi":"https://doi.org/10.1109/tcad.2013.2269768","mag":"1969546595"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2013.2269768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2269768","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058454261","display_name":"Aayush Prakash","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Aayush Prakash","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074065388","display_name":"Hiren Patel","orcid":"https://orcid.org/0000-0003-2750-4471"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Hiren D. Patel","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada]","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.3114,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57327548,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"32","issue":"11","first_page":"1819","last_page":"1823"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8913586139678955},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8144578337669373},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.7282389998435974},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5392763614654541},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.506824791431427},{"id":"https://openalex.org/keywords/worst-case-execution-time","display_name":"Worst-case execution time","score":0.49498337507247925},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47607487440109253},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.4701172113418579},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.46077272295951843},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.43418949842453003},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.41170600056648254},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.3641148805618286},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.17926031351089478},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17792242765426636},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.14811190962791443},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11921510100364685}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8913586139678955},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8144578337669373},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.7282389998435974},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5392763614654541},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.506824791431427},{"id":"https://openalex.org/C200130814","wikidata":"https://www.wikidata.org/wiki/Q362858","display_name":"Worst-case execution time","level":3,"score":0.49498337507247925},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47607487440109253},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4701172113418579},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.46077272295951843},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.43418949842453003},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.41170600056648254},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.3641148805618286},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.17926031351089478},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17792242765426636},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.14811190962791443},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11921510100364685},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2013.2269768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2269768","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:uwspace.uwaterloo.ca:10012/7159","is_oa":false,"landing_page_url":"http://hdl.handle.net/10012/7159","pdf_url":null,"source":{"id":"https://openalex.org/S4306401661","display_name":"UWSpace (University of Waterloo)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I151746483","host_organization_name":"University of Waterloo","host_organization_lineage":["https://openalex.org/I151746483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Master Thesis"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1534602475","https://openalex.org/W2061650414","https://openalex.org/W2102800454","https://openalex.org/W2122833539","https://openalex.org/W2123470671","https://openalex.org/W2132808802","https://openalex.org/W2163270257","https://openalex.org/W2167631583","https://openalex.org/W6631970034"],"related_works":["https://openalex.org/W1515433387","https://openalex.org/W1484796814","https://openalex.org/W2138385884","https://openalex.org/W2507397068","https://openalex.org/W2166895275","https://openalex.org/W2756587144","https://openalex.org/W59945861","https://openalex.org/W2537786014","https://openalex.org/W52215546","https://openalex.org/W1552971043"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,74,82,87,105,123],"static":[4],"instruction":[5],"scratchpad":[6],"memory":[7],"allocation":[8,32,47,64],"scheme":[9,33],"for":[10],"the":[11,23,28,31,38,49,53,58,63,95,98,109,114,117,128],"precision":[12],"timed":[13],"architecture":[14],"(PRET).":[15],"Since":[16],"PRET":[17,59],"provides":[18],"timing":[19,50],"instructions":[20],"to":[21,35,112],"control":[22],"temporal":[24,41],"execution":[25],"of":[26,30,57,108,116],"programs,":[27],"objective":[29],"is":[34],"ensure":[36],"that":[37,76],"explicitly":[39],"specified":[40],"requirements":[42,51],"are":[43],"met.":[44],"Furthermore,":[45],"this":[46],"incorporates":[48],"from":[52,127],"multiple":[54],"hardware":[55],"threads":[56],"architecture.":[60],"We":[61,100,120],"formulate":[62],"problem":[65],"as":[66],"an":[67],"integer-linear":[68],"programming":[69],"problem,":[70],"and":[71,90,93],"we":[72],"implement":[73],"tool":[75],"takes":[77],"compiled":[78],"ARMv4":[79],"binaries,":[80],"constructs":[81],"timing-requirements-aware":[83],"control-flow":[84],"graph,":[85],"performs":[86],"WCET":[88],"analysis":[89],"SPM":[91],"allocation,":[92],"rewrites":[94],"binaries":[96],"with":[97],"allocation.":[99],"evaluate":[101],"our":[102],"approach":[103],"using":[104],"modified":[106],"version":[107],"Malardalen":[110],"benchmarks":[111],"show":[113],"benefits":[115],"proposed":[118],"approach.":[119],"also":[121],"present":[122],"UAV":[124],"benchmark":[125],"derived":[126],"PapaBench":[129],"benchmark.":[130]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
