{"id":"https://openalex.org/W2089597903","doi":"https://doi.org/10.1109/tcad.2013.2252057","title":"Generalized Memristive Device SPICE Model and its Application in Circuit Design","display_name":"Generalized Memristive Device SPICE Model and its Application in Circuit Design","publication_year":2013,"publication_date":"2013-07-15","ids":{"openalex":"https://openalex.org/W2089597903","doi":"https://doi.org/10.1109/tcad.2013.2252057","mag":"2089597903"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2013.2252057","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2252057","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055959085","display_name":"Chris Yakopcic","orcid":"https://orcid.org/0000-0001-6401-272X"},"institutions":[{"id":"https://openalex.org/I127591826","display_name":"University of Dayton","ror":"https://ror.org/021v3qy27","country_code":"US","type":"education","lineage":["https://openalex.org/I127591826"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Yakopcic","raw_affiliation_strings":["University of Dayton, Dayton, OH, USA","University of Dayton , Dayton, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Dayton, Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]},{"raw_affiliation_string":"University of Dayton , Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104090957","display_name":"Tarek M. Taha","orcid":null},"institutions":[{"id":"https://openalex.org/I127591826","display_name":"University of Dayton","ror":"https://ror.org/021v3qy27","country_code":"US","type":"education","lineage":["https://openalex.org/I127591826"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tarek M. Taha","raw_affiliation_strings":["University of Dayton, Dayton, OH, USA","University of Dayton , Dayton, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Dayton, Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]},{"raw_affiliation_string":"University of Dayton , Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037351559","display_name":"Guru Subramanyam","orcid":"https://orcid.org/0000-0003-2871-0277"},"institutions":[{"id":"https://openalex.org/I127591826","display_name":"University of Dayton","ror":"https://ror.org/021v3qy27","country_code":"US","type":"education","lineage":["https://openalex.org/I127591826"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Guru Subramanyam","raw_affiliation_strings":["University of Dayton, Dayton, OH, USA","University of Dayton , Dayton, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Dayton, Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]},{"raw_affiliation_string":"University of Dayton , Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109848389","display_name":"Robinson E. Pino","orcid":null},"institutions":[{"id":"https://openalex.org/I127591826","display_name":"University of Dayton","ror":"https://ror.org/021v3qy27","country_code":"US","type":"education","lineage":["https://openalex.org/I127591826"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robinson E. Pino","raw_affiliation_strings":["University of Dayton, Dayton, OH, USA","University of Dayton , Dayton, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Dayton, Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]},{"raw_affiliation_string":"University of Dayton , Dayton, OH, USA","institution_ids":["https://openalex.org/I127591826"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I127591826"],"apc_list":null,"apc_paid":null,"fwci":12.448,"has_fulltext":false,"cited_by_count":248,"citation_normalized_percentile":{"value":0.98997761,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":"32","issue":"8","first_page":"1201","last_page":"1214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.992900013923645,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.968288242816925},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8506176471710205},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.6584657430648804},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5936301946640015},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5783186554908752},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.47137248516082764},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4423365294933319},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43395593762397766},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.41580620408058167},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.21492674946784973},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.212683767080307},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19912269711494446},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1750170886516571}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.968288242816925},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8506176471710205},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.6584657430648804},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5936301946640015},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5783186554908752},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.47137248516082764},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4423365294933319},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43395593762397766},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.41580620408058167},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.21492674946784973},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.212683767080307},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19912269711494446},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1750170886516571}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2013.2252057","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2013.2252057","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1971556564","https://openalex.org/W1980112987","https://openalex.org/W1981175504","https://openalex.org/W1998385236","https://openalex.org/W2000321316","https://openalex.org/W2003942425","https://openalex.org/W2007898123","https://openalex.org/W2008901850","https://openalex.org/W2013055927","https://openalex.org/W2016564072","https://openalex.org/W2016922062","https://openalex.org/W2018645548","https://openalex.org/W2038303774","https://openalex.org/W2062565854","https://openalex.org/W2069233440","https://openalex.org/W2069418413","https://openalex.org/W2080659521","https://openalex.org/W2108343465","https://openalex.org/W2112181056","https://openalex.org/W2113899638","https://openalex.org/W2114601050","https://openalex.org/W2114719435","https://openalex.org/W2122733133","https://openalex.org/W2129936377","https://openalex.org/W2132762610","https://openalex.org/W2145942961","https://openalex.org/W2148331362","https://openalex.org/W2153251307","https://openalex.org/W2153690880","https://openalex.org/W2154478031","https://openalex.org/W2157729981","https://openalex.org/W2159731583","https://openalex.org/W2161330443","https://openalex.org/W2162651880","https://openalex.org/W2163031927","https://openalex.org/W2170731400","https://openalex.org/W2603064927","https://openalex.org/W3106114372","https://openalex.org/W3151055086","https://openalex.org/W3152310809","https://openalex.org/W6652589295","https://openalex.org/W6678426860","https://openalex.org/W6736339276"],"related_works":["https://openalex.org/W3049246456","https://openalex.org/W2015297467","https://openalex.org/W2035017065","https://openalex.org/W4242780158","https://openalex.org/W4241208885","https://openalex.org/W2323645878","https://openalex.org/W2159731583","https://openalex.org/W2094066961","https://openalex.org/W2767118459","https://openalex.org/W1997629593"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,41,90,111,130],"SPICE":[4],"model":[5,36,48,77,121],"for":[6],"memristive":[7,86],"devices.":[8],"It":[9],"builds":[10],"on":[11,105],"existing":[12,32],"models":[13],"and":[14,60,103],"is":[15,49],"correlated":[16],"against":[17],"several":[18],"published":[19,45],"device":[20,87,99],"characterization":[21],"data":[22],"with":[23,55],"an":[24],"average":[25],"error":[26],"of":[27,44,85,96],"6.04%.":[28],"When":[29],"compared":[30,69],"to":[31,57,64,70,81,125],"alternatives,":[33],"the":[34,76,83,94,120],"proposed":[35],"can":[37,78,122],"more":[38],"accurately":[39],"simulate":[40],"wide":[42],"range":[43],"memristors.":[46],"The":[47],"also":[50],"tested":[51],"in":[52,98,129],"large":[53],"circuits":[54],"up":[56],"256":[58],"memristors,":[59],"was":[61],"less":[62],"likely":[63],"cause":[65],"convergence":[66],"errors":[67],"when":[68],"other":[71],"models.":[72],"We":[73,92],"show":[74,118],"that":[75,119],"be":[79,123],"used":[80,124],"study":[82],"impact":[84,95,134],"variation":[88,128],"within":[89],"circuit.":[91,115],"examine":[93],"nonuniformity":[97],"state":[100],"variable":[101],"dynamics":[102],"conductivity":[104],"individual":[106],"memristors":[107],"as":[108,110],"well":[109],"four":[112],"memristor":[113,131],"read/write":[114],"These":[116],"studies":[117],"predict":[126],"how":[127],"wafer":[132],"may":[133],"circuit":[135],"performance.":[136]},"counts_by_year":[{"year":2026,"cited_by_count":6},{"year":2025,"cited_by_count":12},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":16},{"year":2022,"cited_by_count":24},{"year":2021,"cited_by_count":33},{"year":2020,"cited_by_count":27},{"year":2019,"cited_by_count":27},{"year":2018,"cited_by_count":16},{"year":2017,"cited_by_count":25},{"year":2016,"cited_by_count":16},{"year":2015,"cited_by_count":22},{"year":2014,"cited_by_count":12},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}