{"id":"https://openalex.org/W1972393920","doi":"https://doi.org/10.1109/tcad.2012.2233862","title":"Structure-Aware Placement Techniques for Designs With Datapaths","display_name":"Structure-Aware Placement Techniques for Designs With Datapaths","publication_year":2013,"publication_date":"2013-01-21","ids":{"openalex":"https://openalex.org/W1972393920","doi":"https://doi.org/10.1109/tcad.2012.2233862","mag":"1972393920"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2012.2233862","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2233862","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108425433","display_name":"Samuel I. Ward","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Samuel I. Ward","raw_affiliation_strings":["University of Texas, Austin, TX, USA","University of Texas, Austin, TX. USA"],"affiliations":[{"raw_affiliation_string":"University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"University of Texas, Austin, TX. USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101610666","display_name":"Myungchul Kim","orcid":"https://orcid.org/0000-0001-8077-0053"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Myung-Chul Kim","raw_affiliation_strings":["IBM Corporation, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Corporation, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Natarajan Viswanathan","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Natarajan Viswanathan","raw_affiliation_strings":["IBM Corporation, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Corporation, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100448026","display_name":"Zhuo Li","orcid":"https://orcid.org/0000-0002-5535-5920"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhuo Li","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113656006","display_name":"Charles J. Alpert","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Charles J. Alpert","raw_affiliation_strings":["IBM Austin Research Laboratory, Austin, TX, USA","IBM Austin Research Laboratories, Austin, TX, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"IBM Austin Research Laboratory, Austin, TX, USA","institution_ids":["https://openalex.org/I4210156936"]},{"raw_affiliation_string":"IBM Austin Research Laboratories, Austin, TX, USA#TAB#","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028439610","display_name":"Earl E. Swartzlander","orcid":"https://orcid.org/0000-0002-8699-5277"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Earl E. Swartzlander","raw_affiliation_strings":["University of Texas, Austin, TX, USA","University of Texas, Austin, TX. USA"],"affiliations":[{"raw_affiliation_string":"University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"University of Texas, Austin, TX. USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["University of Texas, Austin, TX, USA","University of Texas, Austin, TX. USA"],"affiliations":[{"raw_affiliation_string":"University of Texas, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"University of Texas, Austin, TX. USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5108425433"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":1.1996,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.80677554,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"32","issue":"2","first_page":"228","last_page":"241"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9662469625473022},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7272469997406006},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6993272304534912},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5653741955757141},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5505132079124451},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5467345714569092},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5254228115081787},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.45406079292297363},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45394471287727356},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.42863041162490845},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41500627994537354},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41449862718582153},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3532658815383911},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35000038146972656},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2618081867694855},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15683051943778992},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1444883644580841}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9662469625473022},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7272469997406006},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6993272304534912},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5653741955757141},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5505132079124451},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5467345714569092},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5254228115081787},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.45406079292297363},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45394471287727356},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.42863041162490845},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41500627994537354},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41449862718582153},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3532658815383911},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35000038146972656},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2618081867694855},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15683051943778992},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1444883644580841},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2012.2233862","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2233862","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1494247570","https://openalex.org/W1580879576","https://openalex.org/W1978226299","https://openalex.org/W1982924274","https://openalex.org/W1986026297","https://openalex.org/W1989931041","https://openalex.org/W1999116995","https://openalex.org/W2002525234","https://openalex.org/W2003145440","https://openalex.org/W2010952387","https://openalex.org/W2011912079","https://openalex.org/W2012450447","https://openalex.org/W2018351041","https://openalex.org/W2031918981","https://openalex.org/W2043643711","https://openalex.org/W2043679008","https://openalex.org/W2055704923","https://openalex.org/W2106468809","https://openalex.org/W2109128256","https://openalex.org/W2111359499","https://openalex.org/W2114136290","https://openalex.org/W2120129706","https://openalex.org/W2133367791","https://openalex.org/W2146232231","https://openalex.org/W2147899388","https://openalex.org/W2161455936","https://openalex.org/W2165972132","https://openalex.org/W2168126808","https://openalex.org/W2169437985","https://openalex.org/W2170259515","https://openalex.org/W2173471405","https://openalex.org/W3151205559","https://openalex.org/W3152105119","https://openalex.org/W4231171283","https://openalex.org/W4233403045","https://openalex.org/W4235188236","https://openalex.org/W6629502487","https://openalex.org/W6658706690","https://openalex.org/W6661169969","https://openalex.org/W6676886990","https://openalex.org/W6684879859"],"related_works":["https://openalex.org/W2121367602","https://openalex.org/W2113599973","https://openalex.org/W2070693700","https://openalex.org/W2120549874","https://openalex.org/W2113434540","https://openalex.org/W2119748374","https://openalex.org/W4233226037","https://openalex.org/W1975649745","https://openalex.org/W2114514951","https://openalex.org/W1996820488"],"abstract_inverted_index":{"As":[0],"technology":[1],"scales":[2],"and":[3,20,38,53,84,100,112,127,172],"frequencies":[4],"increase,":[5],"a":[6,15,74,95,122],"new":[7,75],"hybrid":[8,44,69,197],"design":[9],"style":[10],"emerges,":[11],"wherein":[12],"designs":[13,61,155],"contain":[14],"mixture":[16],"of":[17,36,94,105,114,121,124,149],"random":[18,82],"logic":[19,83],"datapath":[21,64,85,106,184],"standard-cell":[22],"components.":[23],"This":[24,87],"paper":[25,72],"demonstrates":[26],"that":[27,79],"conventional":[28],"half-perimeter":[29],"wirelength":[30,40],"driven":[31],"placers":[32,152],"underperform":[33],"in":[34],"terms":[35],"regularity":[37],"Steiner":[39],"(StWL)":[41],"for":[42],"such":[43],"designs.":[45,198],"In":[46,187],"addition,":[47,188],"the":[48,60,92,103,110,147,181],"quality":[49,104],"gap":[50],"between":[51],"manual":[52],"automatic":[54],"placement":[55,77,107,117,129,134],"is":[56,89],"more":[57,63,169],"pronounced":[58],"as":[59],"become":[62],"oriented.":[65],"To":[66],"effectively":[67,139],"handle":[68],"designs,":[70],"this":[71],"proposes":[73],"unified":[76],"flow":[78,88],"simultaneously":[80],"places":[81],"cells.":[86],"built":[90],"on":[91,180,195],"top":[93],"leading":[96],"academic":[97],"force-directed":[98],"placer":[99],"significantly":[101],"improves":[102,165,190],"while":[108],"leveraging":[109],"speed":[111],"flexibility":[113],"existing":[115,150],"random-logic":[116,151],"algorithms.":[118],"It":[119],"consists":[120],"suite":[123],"novel":[125],"global":[126],"detailed":[128],"techniques,":[130],"collectively":[131],"called":[132],"structure-aware":[133],"techniques":[135,138],"(SAPT).":[136],"These":[137],"integrate":[140],"alignment":[141],"constraints":[142],"into":[143],"placement,":[144],"thereby":[145],"overcoming":[146],"deficiencies":[148],"when":[153],"handling":[154],"with":[156],"embedded":[157],"datapaths.":[158],"Compared":[159],"to":[160],"other":[161],"state-of-the-art":[162],"placers,":[163],"SAPT":[164],"total":[166,173,191],"StWL":[167,192],"by":[168,176,193],"than":[170],"28%":[171],"routing":[174],"overflow":[175],"over":[177],"six":[178],"times":[179],"ISPD":[182],"2011":[183],"benchmark":[185],"suite.":[186],"it":[189],"5.8%":[194],"industrial":[196]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":3}],"updated_date":"2026-04-16T08:26:57.006410","created_date":"2025-10-10T00:00:00"}