{"id":"https://openalex.org/W2094548296","doi":"https://doi.org/10.1109/tcad.2012.2208644","title":"Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs","display_name":"Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs","publication_year":2012,"publication_date":"2012-11-21","ids":{"openalex":"https://openalex.org/W2094548296","doi":"https://doi.org/10.1109/tcad.2012.2208644","mag":"2094548296"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2012.2208644","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2208644","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021549162","display_name":"Katherine Shu-Min Li","orcid":"https://orcid.org/0000-0002-9942-5185"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Katherine Shu-Min Li","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076303510","display_name":"Yi-Yu Liao","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Yu Liao","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5021549162"],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":1.1602,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78892636,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"31","issue":"12","first_page":"1930","last_page":"1934"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6708159446716309},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.647121012210846},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6091234683990479},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5775074362754822},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5054337978363037},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.497952938079834},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.4638635516166687},{"id":"https://openalex.org/keywords/volume","display_name":"Volume (thermodynamics)","score":0.45887863636016846},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4428692162036896},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4356592893600464},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.4254821538925171},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3925553560256958},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3643491864204407},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.35453301668167114},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34317103028297424},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32248955965042114},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.31406348943710327},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17201095819473267},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12568536400794983}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6708159446716309},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.647121012210846},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6091234683990479},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5775074362754822},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5054337978363037},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.497952938079834},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.4638635516166687},{"id":"https://openalex.org/C20556612","wikidata":"https://www.wikidata.org/wiki/Q4469374","display_name":"Volume (thermodynamics)","level":2,"score":0.45887863636016846},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4428692162036896},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4356592893600464},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.4254821538925171},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3925553560256958},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3643491864204407},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.35453301668167114},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34317103028297424},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32248955965042114},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.31406348943710327},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17201095819473267},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12568536400794983},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2012.2208644","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2208644","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Life in Land","score":0.41999998688697815,"id":"https://metadata.un.org/sdg/15"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2004015493","https://openalex.org/W2092035107","https://openalex.org/W2112647513","https://openalex.org/W2114385620","https://openalex.org/W2120960137","https://openalex.org/W2127183717","https://openalex.org/W2134083065","https://openalex.org/W2146594632","https://openalex.org/W2159056656","https://openalex.org/W2163293408","https://openalex.org/W2779073193","https://openalex.org/W6679162273"],"related_works":["https://openalex.org/W2098533503","https://openalex.org/W4285708951","https://openalex.org/W2147986372","https://openalex.org/W2048563045","https://openalex.org/W4230966676","https://openalex.org/W2111803469","https://openalex.org/W2160753176","https://openalex.org/W2520108610","https://openalex.org/W1982916741","https://openalex.org/W2129020400"],"abstract_inverted_index":{"An":[0],"interconnect-driven":[1],"layout-aware":[2,37],"multiple":[3],"scan":[4,20,38],"tree":[5,39],"(MST)":[6],"synthesis":[7,40],"methodology":[8],"for":[9],"3-D":[10,52,67],"integrated":[11],"circuits":[12],"(ICs)":[13],"is":[14],"proposed.":[15],"MSTs,":[16],"also":[17],"known":[18,77],"as":[19],"forest,":[21],"greatly":[22],"reduce":[23],"test":[24,28,60],"data":[25],"volume":[26],"and":[27,63,70],"application":[29],"time":[30],"in":[31],"system-on-a-chip":[32],"testing.":[33],"Previous":[34],"studies":[35],"on":[36],"only":[41],"address":[42],"2-D":[43],"layouts,":[44],"so":[45],"they":[46],"cannot":[47],"be":[48],"directly":[49],"applied":[50],"to":[51],"ICs.":[53],"The":[54],"proposed":[55],"algorithm":[56],"effectively":[57],"optimizes":[58],"both":[59],"compression":[61],"rate":[62],"routing":[64],"length":[65],"under":[66],"IC-induced":[68],"constraints,":[69],"produces":[71],"better":[72],"results":[73],"than":[74],"all":[75],"previous":[76],"methods.":[78]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
