{"id":"https://openalex.org/W2045539242","doi":"https://doi.org/10.1109/tcad.2012.2190069","title":"MARS: Matching-Driven Analog Sizing","display_name":"MARS: Matching-Driven Analog Sizing","publication_year":2012,"publication_date":"2012-07-13","ids":{"openalex":"https://openalex.org/W2045539242","doi":"https://doi.org/10.1109/tcad.2012.2190069","mag":"2045539242"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2012.2190069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2190069","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058266912","display_name":"Michael Eick","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Michael Eick","raw_affiliation_strings":["Institute for Electronic Design Automation, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","Inst. for Electron. Design Autom., Tech. Univ. Munchen, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Inst. for Electron. Design Autom., Tech. Univ. Munchen, Munich, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033163680","display_name":"Helmut Graeb","orcid":"https://orcid.org/0000-0002-7626-1958"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Helmut E. Graeb","raw_affiliation_strings":["Institute for Electronic Design Automation, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","Inst. for Electron. Design Autom., Tech. Univ. Munchen, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation, Technische Universit\u00e4t M\u00fcnchen, Munich, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Inst. for Electron. Design Autom., Tech. Univ. Munchen, Munich, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5058266912"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":2.2095,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.88561642,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"31","issue":"8","first_page":"1145","last_page":"1158"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.9273675680160522},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8549109101295471},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6005608439445496},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.5290680527687073},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5145692229270935},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.51084965467453},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.503391683101654},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45424211025238037},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.340474933385849},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18115228414535522},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1761845350265503},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.14592280983924866},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07291647791862488}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.9273675680160522},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8549109101295471},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6005608439445496},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.5290680527687073},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5145692229270935},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.51084965467453},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.503391683101654},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45424211025238037},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.340474933385849},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18115228414535522},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1761845350265503},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.14592280983924866},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07291647791862488},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2012.2190069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2190069","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W147475332","https://openalex.org/W584099094","https://openalex.org/W1530621902","https://openalex.org/W1552518404","https://openalex.org/W1556472513","https://openalex.org/W1565462788","https://openalex.org/W1577634307","https://openalex.org/W1968850083","https://openalex.org/W1981502496","https://openalex.org/W1998284495","https://openalex.org/W1998752433","https://openalex.org/W2031717999","https://openalex.org/W2076461640","https://openalex.org/W2098364892","https://openalex.org/W2100128641","https://openalex.org/W2114912418","https://openalex.org/W2120889849","https://openalex.org/W2121456807","https://openalex.org/W2126589469","https://openalex.org/W2134152592","https://openalex.org/W2141001531","https://openalex.org/W2142024558","https://openalex.org/W2162964517","https://openalex.org/W2166981698","https://openalex.org/W2184826174","https://openalex.org/W2320198223","https://openalex.org/W2532349549","https://openalex.org/W4237482588","https://openalex.org/W4240491127","https://openalex.org/W4298334616","https://openalex.org/W6642351083"],"related_works":["https://openalex.org/W2170314243","https://openalex.org/W2119179026","https://openalex.org/W2794947590","https://openalex.org/W2114971758","https://openalex.org/W2109932036","https://openalex.org/W2093081283","https://openalex.org/W4313118781","https://openalex.org/W2354546390","https://openalex.org/W2011183285","https://openalex.org/W1962246972"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,19,32,56,61],"new":[4],"approach":[5],"for":[6,12,45],"automatic":[7],"computation":[8],"of":[9,52,68,100,106],"matching":[10],"constraints":[11,28,44],"analog":[13,101],"sizing.":[14],"The":[15],"method":[16,40,65],"automatically":[17],"analyzes":[18],"circuit":[20,54],"netlist":[21],"to":[22,76,84],"generate":[23],"sizing":[24,27,92],"constraints.":[25],"These":[26],"are":[29,109],"considered":[30],"during":[31],"subsequent":[33],"numerical":[34],"optimization.":[35],"It":[36,80],"is":[37,66],"the":[38,49,53,64,98],"first":[39],"that":[41,97],"computes":[42],"symmetry":[43,78],"sizing,":[46,102],"based":[47],"on":[48],"hierarchical":[50],"structure":[51],"and":[55,72,86,89],"qualitative":[57],"signal":[58,71],"flow.":[59],"As":[60],"unique":[62],"feature,":[63],"capable":[67],"handling":[69],"multiple":[70,77],"feedback":[73],"paths,":[74],"leading":[75],"axes.":[79],"can":[81],"be":[82],"applied":[83],"linear":[85],"nonlinear":[87],"circuits":[88],"any":[90],"available":[91],"algorithm.":[93],"Experimental":[94],"results":[95],"show":[96],"runtime":[99],"as":[103,105],"well":[104],"result":[107],"quality,":[108],"greatly":[110],"improved.":[111]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":10},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}