{"id":"https://openalex.org/W2104896848","doi":"https://doi.org/10.1109/tcad.2012.2187206","title":"Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations","display_name":"Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations","publication_year":2012,"publication_date":"2012-06-14","ids":{"openalex":"https://openalex.org/W2104896848","doi":"https://doi.org/10.1109/tcad.2012.2187206","mag":"2104896848"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2012.2187206","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2187206","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101549412","display_name":"Lin Xie","orcid":"https://orcid.org/0000-0001-5385-7380"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lin Xie","raw_affiliation_strings":["Cadence Design Systems, Inc., San Jose, CA, USA","Cadence Design Systems, Inc.,San Jose,CA,USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems, Inc.,San Jose,CA,USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072204999","display_name":"Azadeh Davoodi","orcid":"https://orcid.org/0000-0001-5213-2556"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Davoodi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI, USA","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI, USA#TAB#","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61885945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"31","issue":"7","first_page":"1008","last_page":"1018"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7435280680656433},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.6283559799194336},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.6215108633041382},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6021931767463684},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5970511436462402},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5906973481178284},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5500400066375732},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5355534553527832},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.47109255194664},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4596748650074005},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.414610892534256},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3382192850112915},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.25912490487098694},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.22353145480155945},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2144821286201477},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13032472133636475},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08966413140296936},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.08855995535850525},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07222265005111694}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7435280680656433},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.6283559799194336},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.6215108633041382},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6021931767463684},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5970511436462402},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5906973481178284},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5500400066375732},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5355534553527832},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.47109255194664},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4596748650074005},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.414610892534256},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3382192850112915},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.25912490487098694},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.22353145480155945},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2144821286201477},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13032472133636475},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08966413140296936},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.08855995535850525},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07222265005111694},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2012.2187206","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2187206","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W60929302","https://openalex.org/W203899762","https://openalex.org/W1979194489","https://openalex.org/W2021783304","https://openalex.org/W2060473790","https://openalex.org/W2063392856","https://openalex.org/W2067549952","https://openalex.org/W2073414385","https://openalex.org/W2080832951","https://openalex.org/W2087773252","https://openalex.org/W2090692734","https://openalex.org/W2091024449","https://openalex.org/W2122146819","https://openalex.org/W2137602195","https://openalex.org/W2145314233","https://openalex.org/W2156306402","https://openalex.org/W2158486845","https://openalex.org/W2162484339","https://openalex.org/W2163262735","https://openalex.org/W2167480374","https://openalex.org/W2171383332","https://openalex.org/W2171474236","https://openalex.org/W2294521418","https://openalex.org/W3139542001","https://openalex.org/W3145426189","https://openalex.org/W4230390140","https://openalex.org/W4235221304","https://openalex.org/W4240732800","https://openalex.org/W4249020130","https://openalex.org/W4301014558","https://openalex.org/W6641884055","https://openalex.org/W6672556086","https://openalex.org/W6680272670"],"related_works":["https://openalex.org/W2378211422","https://openalex.org/W2745001401","https://openalex.org/W4321353415","https://openalex.org/W2130974462","https://openalex.org/W972276598","https://openalex.org/W4246352526","https://openalex.org/W2028665553","https://openalex.org/W2086519370","https://openalex.org/W2087343574","https://openalex.org/W2121910908"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,12,40,47,76,84,159],"novel":[4],"approach":[5],"for":[6,11,80,149,190],"isolating":[7,145],"the":[8,20,23,27,31,57,65,70,95,107,110,118,126,129,133,146,170,180,191,199,208,213,219,224],"failing":[9,81,136,147,163,201,210,226],"paths":[10,16,21,53,61,89,100,124,137,148,164,178,202,211,222,227],"fabricated":[13,151,197],"chip.":[14,152],"Failing":[15],"are":[17,54,62,90,203],"defined":[18],"as":[19],"violating":[22],"timing":[24,71],"constraint":[25],"at":[26,56,125],"post-silicon":[28,127,130,171],"stage,":[29,128],"in":[30,44,94,179,212],"presence":[32,181],"of":[33,50,87,109,120,132,173,182,218],"process":[34,187],"variations.":[35],"To":[36],"achieve":[37],"this":[38],"goal,":[39],"framework":[41],"is":[42,228],"suggested":[43],"which,":[45],"first,":[46],"large":[48],"number":[49],"statistically":[51,112],"critical":[52,113],"extracted":[55],"pre-silicon":[58],"stage.":[59],"These":[60,98],"those":[63,93],"with":[64,106],"highest":[66],"probability":[67],"to":[68,158,205,230],"violate":[69],"and":[72],"therefore":[73],"can":[74,138,165],"form":[75],"\u201cgood\u201d":[77],"candidate":[78,96,135,162,214],"set":[79,86],"paths.":[82,114],"Next,":[83],"small":[85],"representative":[88,123,177],"selected":[91,99,122],"from":[92,223],"set.":[97,215],"have":[101],"their":[102],"delays":[103,108,119,131,172],"highly":[104],"correlated":[105],"remaining":[111,134],"By":[115],"directly":[116],"measuring":[117],"these":[121],"be":[139,166,231],"predicted":[140,168],"accurately":[141,167],"that":[142,156],"allows":[143],"further":[144],"each":[150,196],"Simulation":[153],"results":[154],"show":[155],"up":[157],"few":[160],"thousand":[161],"using":[169],"less":[174],"than":[175,184],"150":[176],"more":[183],"1000":[185],"independent":[186],"parameter":[188],"variations":[189],"ISCAS89":[192],"benchmark":[193],"circuits.":[194],"For":[195],"chip,":[198],"isolated":[200,225],"guaranteed":[204],"include":[206],"all":[207],"\u201cactual\u201d":[209,220],"The":[216],"proportion":[217],"nonfailing":[221],"shown":[229],"very":[232],"small.":[233]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}