{"id":"https://openalex.org/W2010202670","doi":"https://doi.org/10.1109/tcad.2012.2185930","title":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory","display_name":"NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory","publication_year":2012,"publication_date":"2012-06-14","ids":{"openalex":"https://openalex.org/W2010202670","doi":"https://doi.org/10.1109/tcad.2012.2185930","mag":"2010202670"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2012.2185930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2185930","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083960440","display_name":"Xiangyu Dong","orcid":"https://orcid.org/0009-0003-5638-7558"},"institutions":[{"id":"https://openalex.org/I19268510","display_name":"Qualcomm (United Kingdom)","ror":"https://ror.org/04d3djg48","country_code":"GB","type":"company","lineage":["https://openalex.org/I19268510","https://openalex.org/I4210087596"]},{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]},{"id":"https://openalex.org/I4210111675","display_name":"Market Matters","ror":"https://ror.org/021yan307","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I4210111675"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Xiangyu Dong","raw_affiliation_strings":["Qualcomm, Inc., San Diego, CA, USA","Qualcomm Inc.  San Diego CA USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]},{"raw_affiliation_string":"Qualcomm Inc.  San Diego CA USA","institution_ids":["https://openalex.org/I19268510","https://openalex.org/I4210111675"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101777595","display_name":"Cong Xu","orcid":"https://orcid.org/0000-0002-9278-1363"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cong Xu","raw_affiliation_strings":["Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","Department of Computer Science and Engineering Pennsylvania State University  University Park PA USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Department of Computer Science and Engineering Pennsylvania State University  University Park PA USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100385336","display_name":"Yuan Xie","orcid":"https://orcid.org/0000-0003-2093-1788"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","Department of Computer Science and Engineering Pennsylvania State University  University Park PA USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Department of Computer Science and Engineering Pennsylvania State University  University Park PA USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050207942","display_name":"Norman P. Jouppi","orcid":"https://orcid.org/0000-0003-1765-1929"},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. P. Jouppi","raw_affiliation_strings":["Intelligent Infrastructure Laboratory, Hewlett Packard Laboratory, Palo Alto, CA, USA","Intell. Infrastruct. Lab., Hewlett-Packard Labs., Palo Alto, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intelligent Infrastructure Laboratory, Hewlett Packard Laboratory, Palo Alto, CA, USA","institution_ids":["https://openalex.org/I1324840837","https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intell. Infrastruct. Lab., Hewlett-Packard Labs., Palo Alto, CA, USA","institution_ids":["https://openalex.org/I1324840837","https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":43.4881,"has_fulltext":false,"cited_by_count":1210,"citation_normalized_percentile":{"value":0.99901886,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":"31","issue":"7","first_page":"994","last_page":"1007"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11315","display_name":"Phase-change materials and chalcogenides","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2505","display_name":"Materials Chemistry"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.7630184888839722},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.756672739982605},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.7033196687698364},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6311201453208923},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6092535853385925},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6054019927978516},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.566802442073822},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.5482259392738342},{"id":"https://openalex.org/keywords/racetrack-memory","display_name":"Racetrack memory","score":0.5425369143486023},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5316296815872192},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.4727809429168701},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4590979218482971},{"id":"https://openalex.org/keywords/phase-change-memory","display_name":"Phase-change memory","score":0.44773736596107483},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.41429659724235535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4100490212440491},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3665686845779419},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30466923117637634},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.20349276065826416},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19052129983901978},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.11470162868499756},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.10611668229103088},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10339638590812683},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09831959009170532},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.08719906210899353}],"concepts":[{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.7630184888839722},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.756672739982605},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.7033196687698364},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6311201453208923},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6092535853385925},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6054019927978516},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.566802442073822},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.5482259392738342},{"id":"https://openalex.org/C43363307","wikidata":"https://www.wikidata.org/wiki/Q1651623","display_name":"Racetrack memory","level":5,"score":0.5425369143486023},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5316296815872192},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.4727809429168701},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4590979218482971},{"id":"https://openalex.org/C64142963","wikidata":"https://www.wikidata.org/wiki/Q1153902","display_name":"Phase-change memory","level":3,"score":0.44773736596107483},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.41429659724235535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4100490212440491},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3665686845779419},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30466923117637634},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.20349276065826416},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19052129983901978},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.11470162868499756},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.10611668229103088},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10339638590812683},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09831959009170532},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.08719906210899353},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2012.2185930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2012.2185930","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-133743","is_oa":false,"landing_page_url":"http://www.scopus.com/record/display.url?eid=2-s2.0-84862685650&origin=inward","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7599999904632568,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":60,"referenced_works":["https://openalex.org/W1497430048","https://openalex.org/W1500829088","https://openalex.org/W1904881491","https://openalex.org/W1970221984","https://openalex.org/W1985868795","https://openalex.org/W1987201308","https://openalex.org/W2007300900","https://openalex.org/W2008904077","https://openalex.org/W2013055927","https://openalex.org/W2032091965","https://openalex.org/W2035257891","https://openalex.org/W2037747688","https://openalex.org/W2039632601","https://openalex.org/W2040094671","https://openalex.org/W2052677323","https://openalex.org/W2069367007","https://openalex.org/W2072730350","https://openalex.org/W2078260102","https://openalex.org/W2085273892","https://openalex.org/W2088115909","https://openalex.org/W2096800126","https://openalex.org/W2099856791","https://openalex.org/W2100799944","https://openalex.org/W2102255233","https://openalex.org/W2105408739","https://openalex.org/W2107012212","https://openalex.org/W2109143217","https://openalex.org/W2113512876","https://openalex.org/W2119668988","https://openalex.org/W2122435992","https://openalex.org/W2127219199","https://openalex.org/W2134473475","https://openalex.org/W2138661001","https://openalex.org/W2148831941","https://openalex.org/W2150073849","https://openalex.org/W2155370145","https://openalex.org/W2155551886","https://openalex.org/W2156560114","https://openalex.org/W2160814308","https://openalex.org/W2165310699","https://openalex.org/W2168972302","https://openalex.org/W2169405529","https://openalex.org/W2407083426","https://openalex.org/W2539856142","https://openalex.org/W2543205889","https://openalex.org/W3099470245","https://openalex.org/W3137284226","https://openalex.org/W3144954235","https://openalex.org/W3145579537","https://openalex.org/W3146544365","https://openalex.org/W6629935286","https://openalex.org/W6652408048","https://openalex.org/W6659307720","https://openalex.org/W6675347859","https://openalex.org/W6676450090","https://openalex.org/W6677974574","https://openalex.org/W6682017485","https://openalex.org/W6684474170","https://openalex.org/W6728840518","https://openalex.org/W6729029536"],"related_works":["https://openalex.org/W2473964774","https://openalex.org/W1993178305","https://openalex.org/W1494152240","https://openalex.org/W2171888576","https://openalex.org/W4387251459","https://openalex.org/W1030357071","https://openalex.org/W2028830162","https://openalex.org/W2188534734","https://openalex.org/W2903040985","https://openalex.org/W1603190074"],"abstract_inverted_index":{"Various":[0],"new":[1,13],"nonvolatile":[2],"memory":[3,18,24,29,55,74],"(NVM)":[4],"technologies":[5],"have":[6],"emerged":[7],"recently.":[8],"Among":[9],"all":[10],"the":[11,34,39,54,62,69],"investigated":[12],"NVM":[14,44,64,99,115,124,140],"candidate":[15],"technologies,":[16,125],"spin-torque-transfer":[17],"(STT-RAM,":[19],"or":[20],"MRAM),":[21],"phase-change":[22],"random-access":[23,28],"(PCRAM),":[25],"and":[26,67,118,130,142],"resistive":[27],"(ReRAM)":[30],"are":[31,90,101],"regarded":[32],"as":[33,92],"most":[35],"promising":[36],"candidates.":[37],"As":[38],"ultimate":[40],"goal":[41],"of":[42],"this":[43,106],"research":[45],"is":[46,58,135,144],"to":[47,60,81,146],"deploy":[48],"them":[49],"into":[50],"multiple":[51],"levels":[52,76],"in":[53,105],"hierarchy,":[56],"it":[57,143],"necessary":[59],"explore":[61],"wide":[63],"design":[65,94],"space":[66],"find":[68],"proper":[70],"implementation":[71],"at":[72],"different":[73],"hierarchy":[75],"from":[77],"highly":[78,82],"latency-optimized":[79],"caches":[80],"density-":[83],"optimized":[84],"secondary":[85],"storage.":[86],"While":[87],"abundant":[88],"tools":[89,97],"available":[91],"SRAM/DRAM":[93],"assistants,":[95],"similar":[96],"for":[98,114],"designs":[100],"currently":[102],"missing.":[103],"Thus,":[104],"paper,":[107],"we":[108],"develop":[109],"NVSim,":[110],"a":[111],"circuit-level":[112],"model":[113],"performance,":[116],"energy,":[117],"area":[119],"estimation,":[120],"which":[121],"supports":[122],"various":[123],"including":[126],"STT-RAM,":[127],"PCRAM,":[128],"ReRAM,":[129],"legacy":[131],"NAND":[132],"Flash.":[133],"NVSim":[134],"successfully":[136],"validated":[137],"against":[138],"industrial":[139],"prototypes,":[141],"expected":[145],"help":[147],"boost":[148],"architecture-level":[149],"NVM-related":[150],"studies.":[151]},"counts_by_year":[{"year":2026,"cited_by_count":21},{"year":2025,"cited_by_count":63},{"year":2024,"cited_by_count":82},{"year":2023,"cited_by_count":77},{"year":2022,"cited_by_count":82},{"year":2021,"cited_by_count":85},{"year":2020,"cited_by_count":119},{"year":2019,"cited_by_count":135},{"year":2018,"cited_by_count":135},{"year":2017,"cited_by_count":111},{"year":2016,"cited_by_count":96},{"year":2015,"cited_by_count":87},{"year":2014,"cited_by_count":71},{"year":2013,"cited_by_count":39},{"year":2012,"cited_by_count":7}],"updated_date":"2026-08-08T01:25:22.217667","created_date":"2025-10-10T00:00:00"}