{"id":"https://openalex.org/W2090589647","doi":"https://doi.org/10.1109/tcad.2011.2181848","title":"An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip","display_name":"An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip","publication_year":2012,"publication_date":"2012-04-20","ids":{"openalex":"https://openalex.org/W2090589647","doi":"https://doi.org/10.1109/tcad.2011.2181848","mag":"2090589647"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2181848","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2181848","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005484411","display_name":"Hassan Salamy","orcid":"https://orcid.org/0000-0003-1314-1702"},"institutions":[{"id":"https://openalex.org/I13511017","display_name":"Texas State University","ror":"https://ror.org/05h9q1g27","country_code":"US","type":"education","lineage":["https://openalex.org/I13511017"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hassan Salamy","raw_affiliation_strings":["Department of Electrical Engineering, Ingram School of Engineering, Texas State University, San Marcos, San Marcos, TX, USA","Dept. of Electr. Eng., Texas State Univ., San Marcos, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Ingram School of Engineering, Texas State University, San Marcos, San Marcos, TX, USA","institution_ids":["https://openalex.org/I13511017"]},{"raw_affiliation_string":"Dept. of Electr. Eng., Texas State Univ., San Marcos, TX, USA","institution_ids":["https://openalex.org/I13511017"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057117526","display_name":"J. Ramanujam","orcid":"https://orcid.org/0000-0002-4349-1327"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Ramanujam","raw_affiliation_strings":["Department of Electrical and Computer Engineering and the Center for Computation and Technology, Louisiana State University, Baton Rouge, LA, USA","Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering and the Center for Computation and Technology, Louisiana State University, Baton Rouge, LA, USA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA","institution_ids":["https://openalex.org/I121820613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7575,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.84736414,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"31","issue":"5","first_page":"717","last_page":"725"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.882638692855835},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8358463048934937},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7300140261650085},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.667556643486023},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.644778311252594},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5146620869636536},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5055429935455322},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47598472237586975},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4398486316204071},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4250168800354004},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.42491552233695984},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3421942889690399},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15794041752815247},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.10821634531021118}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.882638692855835},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8358463048934937},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7300140261650085},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.667556643486023},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.644778311252594},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5146620869636536},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5055429935455322},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47598472237586975},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4398486316204071},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4250168800354004},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.42491552233695984},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3421942889690399},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15794041752815247},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.10821634531021118},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2011.2181848","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2181848","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:repository.lsu.edu:eecs_pubs-2597","is_oa":false,"landing_page_url":"https://repository.lsu.edu/eecs_pubs/1595","pdf_url":null,"source":{"id":"https://openalex.org/S4210169993","display_name":"Civil War Book Review","issn_l":"1528-6592","issn":["1528-6592"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310315936","host_organization_name":"Louisiana State University","host_organization_lineage":["https://openalex.org/P4310315936"],"host_organization_lineage_names":["Louisiana State University"],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Faculty Publications","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1514004212","https://openalex.org/W1686420892","https://openalex.org/W1816728452","https://openalex.org/W1969288309","https://openalex.org/W1973531467","https://openalex.org/W2053444453","https://openalex.org/W2054732504","https://openalex.org/W2086807722","https://openalex.org/W2096232911","https://openalex.org/W2104225326","https://openalex.org/W2105778948","https://openalex.org/W2113870209","https://openalex.org/W2117285153","https://openalex.org/W2131548569","https://openalex.org/W2136453233","https://openalex.org/W2147116847","https://openalex.org/W2153798033","https://openalex.org/W2161147079","https://openalex.org/W2163270257","https://openalex.org/W2506983566","https://openalex.org/W4233673249","https://openalex.org/W4236022842","https://openalex.org/W4237039059","https://openalex.org/W4249006057","https://openalex.org/W4255817501","https://openalex.org/W6637151178"],"related_works":["https://openalex.org/W4281711577","https://openalex.org/W2106200299","https://openalex.org/W2178653557","https://openalex.org/W2520291760","https://openalex.org/W2540211551","https://openalex.org/W2391376741","https://openalex.org/W1976459683","https://openalex.org/W2994908368","https://openalex.org/W2502691491","https://openalex.org/W1976012348"],"abstract_inverted_index":{"The":[0],"growing":[1],"trend":[2],"in":[3,116],"current":[4],"complex":[5],"embedded":[6,64,98,154],"systems":[7,65,88],"is":[8],"to":[9,44,141,147],"deploy":[10],"a":[11,23,125],"multiprocessor":[12],"system-on-chip":[13],"(MPSoC).":[14],"A":[15],"MPSoC":[16],"consists":[17],"of":[18,49,84,96,153],"multiple":[19],"heterogeneous":[20],"processing":[21],"elements,":[22],"memory":[24],"hierarchy,":[25],"and":[26,61,79,103,144],"input/output":[27],"components":[28],"which":[29],"are":[30,77,112,121],"linked":[31],"together":[32],"by":[33],"an":[34,39,97,138],"on-chip":[35],"interconnect":[36],"structure.":[37],"Such":[38],"architecture":[40],"provides":[41],"the":[42,46,54,81,94,101,105,150,162],"flexibility":[43],"meet":[45],"performance":[47],"requirements":[48],"multimedia":[50],"applications":[51,85],"while":[52],"respecting":[53],"constraints":[55],"on":[56,86,100,157],"memory,":[57],"cost,":[58],"size,":[59],"time,":[60],"power.":[62],"Many":[63],"employ":[66],"software-managed":[67],"memories":[68,72],"known":[69],"as":[70],"scratch-pad":[71],"(SPM).":[73],"Unlike":[74],"caches,":[75],"SPMs":[76],"software-controlled":[78],"hence":[80],"execution":[82,151],"time":[83,152],"such":[87,117,124],"can":[89],"be":[90],"accurately":[91],"predicted.":[92],"Scheduling":[93],"tasks":[95],"application":[99],"processors":[102,111],"partitioning":[104,146],"available":[106],"SPM":[107,145],"budget":[108],"among":[109],"these":[110,120],"two":[113],"critical":[114],"issues":[115],"systems.":[118],"Often,":[119],"considered":[122],"separately;":[123],"decoupled":[126],"approach":[127,140],"may":[128],"miss":[129],"better":[130],"quality":[131],"schedules.":[132],"In":[133],"this":[134],"paper,":[135],"we":[136],"present":[137],"integrated":[139],"task":[142],"scheduling":[143],"further":[148],"reduce":[149],"applications.":[155],"Results":[156],"several":[158],"real-life":[159],"benchmarks":[160],"show":[161],"significant":[163],"improvement":[164],"from":[165],"our":[166],"proposed":[167],"technique.":[168]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
