{"id":"https://openalex.org/W2011647964","doi":"https://doi.org/10.1109/tcad.2011.2173491","title":"Integrated Clock Mesh Synthesis With Incremental Register Placement","display_name":"Integrated Clock Mesh Synthesis With Incremental Register Placement","publication_year":2012,"publication_date":"2012-01-30","ids":{"openalex":"https://openalex.org/W2011647964","doi":"https://doi.org/10.1109/tcad.2011.2173491","mag":"2011647964"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2173491","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2173491","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029213009","display_name":"Jianchao Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Jianchao Lu","raw_affiliation_strings":["Synopsys, Inc., Mountain View, CA, USA","Synopsys, Inc. Mountain View, CA USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys, Inc. Mountain View, CA USA","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039413514","display_name":"Xiaomi Mao","orcid":null},"institutions":[{"id":"https://openalex.org/I1342911587","display_name":"Oracle (United States)","ror":"https://ror.org/006c77m33","country_code":"US","type":"company","lineage":["https://openalex.org/I1342911587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaomi Mao","raw_affiliation_strings":["Oracle, Inc., Santa Clara, CA, USA","[Oracle, Inc., Santa Clara, CA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Oracle, Inc., Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1342911587"]},{"raw_affiliation_string":"[Oracle, Inc., Santa Clara, CA, USA]","institution_ids":["https://openalex.org/I1342911587"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","Dept. of Electr. & Comput. Eng. Drexel Univ., Philadelphia, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng. Drexel Univ., Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2098,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.88347425,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"31","issue":"2","first_page":"217","last_page":"227"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.698265552520752},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5764453411102295},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5672070384025574},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5577855706214905},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5108287334442139},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5053804516792297},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.48516517877578735},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4770868718624115},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42754191160202026},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3293072581291199},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.2184029519557953},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19482755661010742},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18854624032974243},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13259801268577576}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.698265552520752},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5764453411102295},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5672070384025574},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5577855706214905},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5108287334442139},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5053804516792297},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.48516517877578735},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4770868718624115},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42754191160202026},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3293072581291199},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.2184029519557953},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19482755661010742},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18854624032974243},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13259801268577576},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2173491","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2173491","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W73629738","https://openalex.org/W1540004773","https://openalex.org/W1966210343","https://openalex.org/W1979163729","https://openalex.org/W1984588379","https://openalex.org/W1985843314","https://openalex.org/W2032024709","https://openalex.org/W2032842232","https://openalex.org/W2041950850","https://openalex.org/W2076139224","https://openalex.org/W2078453114","https://openalex.org/W2105750636","https://openalex.org/W2105844603","https://openalex.org/W2106292145","https://openalex.org/W2115468286","https://openalex.org/W2121252299","https://openalex.org/W2125692303","https://openalex.org/W2128237591","https://openalex.org/W2132075265","https://openalex.org/W2133916137","https://openalex.org/W2144758504","https://openalex.org/W2149199452","https://openalex.org/W3143262395","https://openalex.org/W3183881215","https://openalex.org/W4229863931","https://openalex.org/W4230442644","https://openalex.org/W4240582731","https://openalex.org/W4254534263","https://openalex.org/W6632308595","https://openalex.org/W6644953914","https://openalex.org/W6676046063","https://openalex.org/W6678201958"],"related_works":["https://openalex.org/W4247180033","https://openalex.org/W2088914741","https://openalex.org/W2559451387","https://openalex.org/W2040807843","https://openalex.org/W2556166322","https://openalex.org/W1999924508","https://openalex.org/W4249038728","https://openalex.org/W2144282137","https://openalex.org/W2151287729","https://openalex.org/W2803012234"],"abstract_inverted_index":{"A":[0],"clock":[1,113],"mesh":[2,54],"planning":[3],"and":[4,23,36,58,60,72,95,115],"synthesis":[5],"method":[6,29,80],"is":[7,30],"proposed":[8,28,79],"which":[9],"significantly":[10],"reduces":[11],"the":[12,16,20,33,78,82,89,96,112,118,123],"power":[13,21,70,84,93],"dissipation":[14],"on":[15,86,88,122],"network":[17],"while":[18],"considering":[19,50,69],"density":[22,71],"timing":[24,51,73,99,108],"slack":[25,109],"simultaneously.":[26],"The":[27,75],"performed":[31],"at":[32],"postplacement":[34],"stage":[35],"consists":[37],"of":[38,47,77,111],"three":[39],"major":[40],"steps:":[41],"1)":[42],"feasible":[43],"moving":[44],"region":[45],"construction":[46],"each":[48],"register":[49,63],"slack;":[52],"2)":[53],"grid":[55],"wire":[56,67],"generation":[57],"placement;":[59],"3)":[61],"incremental":[62],"placement":[64],"for":[65],"stub":[66],"minimization":[68],"slack.":[74,100],"advantages":[76,102],"are":[81,103],"reduced":[83],"dissipation-28%":[85],"average":[87],"benchmark":[90,124],"circuits-the":[91],"optimized":[92],"density,":[94],"guaranteed":[97],"nonnegative":[98],"These":[101],"possible":[104],"through":[105],"a":[106],"decreased":[107],"(1.1%":[110],"period)":[114],"change":[116],"in":[117],"logic":[119],"wirelength":[120],"(+5.9%)":[121],"circuits.":[125]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}