{"id":"https://openalex.org/W2085189212","doi":"https://doi.org/10.1109/tcad.2011.2173199","title":"&lt;formula formulatype=\"inline\"&gt;&lt;tex Notation=\"TeX\"&gt;${\\rm SPICE}^2$&lt;/tex&gt;&lt;/formula&gt;: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA","display_name":"&lt;formula formulatype=\"inline\"&gt;&lt;tex Notation=\"TeX\"&gt;${\\rm SPICE}^2$&lt;/tex&gt;&lt;/formula&gt;: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA","publication_year":2011,"publication_date":"2011-12-22","ids":{"openalex":"https://openalex.org/W2085189212","doi":"https://doi.org/10.1109/tcad.2011.2173199","mag":"2085189212"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2173199","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2173199","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://dr.ntu.edu.sg/bitstream/10356/81197/1/Spatial%20Processors%20Interconnected%20for%20Concurrent%20Execution%20for%20Accelerating%20the%20SPICE%20Circuit%20Simulator%20Using%20an%20FPGA.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015534628","display_name":"Nachiket Kapre","orcid":"https://orcid.org/0000-0002-2187-0406"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Nachiket Kapre","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Imperial College London, London, UK","Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Imperial College London, London, UK","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Dept. of Electr. & Electron. Eng., Imperial Coll., London, London, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087585086","display_name":"Andr\u00e9 DeHon","orcid":"https://orcid.org/0000-0001-9177-7699"},"institutions":[{"id":"https://openalex.org/I79576946","display_name":"University of Pennsylvania","ror":"https://ror.org/00b30xv10","country_code":"US","type":"education","lineage":["https://openalex.org/I79576946"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 DeHon","raw_affiliation_strings":["Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA","Dept. of Electr. & Syst. Eng., Univ. of Pennsylvania, Philadelphia, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I79576946"]},{"raw_affiliation_string":"Dept. of Electr. & Syst. Eng., Univ. of Pennsylvania, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I79576946"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.2879,"has_fulltext":true,"cited_by_count":29,"citation_normalized_percentile":{"value":0.92669368,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"31","issue":"1","first_page":"9","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.9112391471862793},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7350566387176514},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.690211296081543},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6206377744674683},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5968510508537292},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.5930317044258118},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.5111721158027649},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.4251832962036133},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.4105972647666931},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2688126266002655}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.9112391471862793},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7350566387176514},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.690211296081543},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6206377744674683},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5968510508537292},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.5930317044258118},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.5111721158027649},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.4251832962036133},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.4105972647666931},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2688126266002655},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2011.2173199","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2173199","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:dr.ntu.edu.sg:10356/81197","is_oa":true,"landing_page_url":"http://hdl.handle.net/10220/39201","pdf_url":"https://dr.ntu.edu.sg/bitstream/10356/81197/1/Spatial%20Processors%20Interconnected%20for%20Concurrent%20Execution%20for%20Accelerating%20the%20SPICE%20Circuit%20Simulator%20Using%20an%20FPGA.pdf","source":{"id":"https://openalex.org/S4306402609","display_name":"DR-NTU (Nanyang Technological University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172675005","host_organization_name":"Nanyang Technological University","host_organization_lineage":["https://openalex.org/I172675005"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Journal Article"}],"best_oa_location":{"id":"pmh:oai:dr.ntu.edu.sg:10356/81197","is_oa":true,"landing_page_url":"http://hdl.handle.net/10220/39201","pdf_url":"https://dr.ntu.edu.sg/bitstream/10356/81197/1/Spatial%20Processors%20Interconnected%20for%20Concurrent%20Execution%20for%20Accelerating%20the%20SPICE%20Circuit%20Simulator%20Using%20an%20FPGA.pdf","source":{"id":"https://openalex.org/S4306402609","display_name":"DR-NTU (Nanyang Technological University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I172675005","host_organization_name":"Nanyang Technological University","host_organization_lineage":["https://openalex.org/I172675005"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Journal Article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2085189212.pdf","grobid_xml":"https://content.openalex.org/works/W2085189212.grobid-xml"},"referenced_works_count":51,"referenced_works":["https://openalex.org/W83535271","https://openalex.org/W107275210","https://openalex.org/W238365506","https://openalex.org/W1503406254","https://openalex.org/W1555915743","https://openalex.org/W1939228150","https://openalex.org/W1974610062","https://openalex.org/W1985788277","https://openalex.org/W1988888548","https://openalex.org/W2007480409","https://openalex.org/W2020561008","https://openalex.org/W2020732682","https://openalex.org/W2024612992","https://openalex.org/W2028666880","https://openalex.org/W2035080386","https://openalex.org/W2040128025","https://openalex.org/W2068028029","https://openalex.org/W2080794684","https://openalex.org/W2085612442","https://openalex.org/W2086987027","https://openalex.org/W2101571719","https://openalex.org/W2105158708","https://openalex.org/W2109139651","https://openalex.org/W2117422942","https://openalex.org/W2129069173","https://openalex.org/W2137165269","https://openalex.org/W2139030761","https://openalex.org/W2139340904","https://openalex.org/W2143162783","https://openalex.org/W2144430894","https://openalex.org/W2147753626","https://openalex.org/W2152406824","https://openalex.org/W2152872804","https://openalex.org/W2153793450","https://openalex.org/W2155946985","https://openalex.org/W2160106215","https://openalex.org/W2166214095","https://openalex.org/W2167078995","https://openalex.org/W2170116489","https://openalex.org/W2788962374","https://openalex.org/W3147150317","https://openalex.org/W3148527039","https://openalex.org/W3151107490","https://openalex.org/W3169463464","https://openalex.org/W4229712245","https://openalex.org/W4236838539","https://openalex.org/W4236878882","https://openalex.org/W4249868603","https://openalex.org/W4285719527","https://openalex.org/W6657484765","https://openalex.org/W6680095847"],"related_works":["https://openalex.org/W2983282793","https://openalex.org/W2159570675","https://openalex.org/W1497152074","https://openalex.org/W3015604234","https://openalex.org/W2074226157","https://openalex.org/W1904802460","https://openalex.org/W2791534362","https://openalex.org/W963568387","https://openalex.org/W2896223349","https://openalex.org/W2103902311"],"abstract_inverted_index":{"Spatial":[0],"processing":[1,138],"of":[2,20,121,126,132,139,156,163,182,210],"sparse,":[3],"irregular,":[4],"double-precision":[5],"floating-point":[6],"computation":[7],"using":[8],"a":[9,27,37,73,94,119,153,161,178,190,217],"single":[10],"field-programmable":[11],"gate":[12],"array":[13],"(FPGA)":[14],"enables":[15],"up":[16],"to":[17,48,98,113,118,213],"an":[18,197,222],"order":[19],"magnitude":[21],"speedup":[22,181],"(mean":[23],"2.8\u00d7":[24],"speedup)":[25],"over":[26],"conventional":[28,115],"microprocessor":[29],"for":[30,43,76,184],"the":[31,45,55,100,140,185],"SPICE":[32,46,60],"circuit":[33],"simulator.":[34],"We":[35,143,204],"develop":[36],"parallel,":[38],"FPGA-based,":[39],"heterogeneous":[40,81],"architecture":[41,75,110],"customized":[42],"accelerating":[44],"simulator":[47],"deliver":[49],"this":[50],"speedup.":[51],"To":[52],"properly":[53],"parallelize":[54],"complete":[56],"simulator,":[57],"we":[58,146],"decompose":[59],"into":[61,93],"its":[62],"three":[63],"constituent":[64],"phases-model":[65],"evaluation,":[66],"sparse":[67],"matrix-solve,":[68],"and":[69,90,135,167],"iteration":[70],"control-and":[71],"customize":[72],"spatial":[74],"each":[77],"phase":[78],"independently.":[79],"Our":[80],"FPGA":[82,109],"organization":[83],"mixes":[84],"very":[85],"large":[86],"instruction":[87],"word,":[88],"dataflow":[89,130],"streaming":[91],"architectures":[92],"cohesive,":[95],"unified":[96],"design":[97,187],"match":[99],"parallel":[101],"patterns":[102],"exposed":[103],"by":[104,152,170],"our":[105],"programming":[106],"framework.":[107],"This":[108],"is":[111],"able":[112],"outperform":[114],"processors":[116],"due":[117],"combination":[120],"factors,":[122],"including":[123],"high":[124],"utilization":[125],"statically-scheduled":[127],"resources,":[128],"low-overhead":[129],"scheduling":[131],"fine-grained":[133],"tasks,":[134],"streaming,":[136],"overlapped":[137],"control":[141],"algorithms.":[142],"demonstrate":[144],"that":[145],"can":[147],"independently":[148],"accelerate":[149],"model":[150],"evaluation":[151],"mean":[154,179,207],"factor":[155],"6.5":[157],"\u00d7":[158],"(1.4-23\u00d7)":[159],"across":[160,172],"range":[162],"nonlinear":[164],"device":[165],"models":[166],"matrix":[168],"solve":[169],"2.4\u00d7(0.6-13\u00d7)":[171],"various":[173],"benchmark":[174],"matrices":[175],"while":[176],"delivering":[177],"combined":[180],"2.8\u00d7(0.2-11\u00d7)":[183],"composite":[186],"when":[188,215],"comparing":[189,216],"Xilinx":[191,218],"Virtex-6":[192,219],"LX760":[193,220],"(40":[194],"nm)":[195],"with":[196,221],"Intel":[198,223],"Core":[199,224],"i7":[200,225],"965":[201],"(45":[202],"nm).":[203],"also":[205],"estimate":[206],"energy":[208],"savings":[209],"8.9\u00d7":[211],"(up":[212],"40.9\u00d7)":[214],"965.":[226]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
