{"id":"https://openalex.org/W2164242767","doi":"https://doi.org/10.1109/tcad.2011.2171963","title":"Synthesis of Active-Mode Power-Gating Circuits","display_name":"Synthesis of Active-Mode Power-Gating Circuits","publication_year":2012,"publication_date":"2012-02-22","ids":{"openalex":"https://openalex.org/W2164242767","doi":"https://doi.org/10.1109/tcad.2011.2171963","mag":"2164242767"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2171963","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2171963","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039958474","display_name":"Jun Seomun","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jun Seomun","raw_affiliation_strings":["Samsung Electronics Limited, Yongin si, Gyeonggi-Do, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics Limited, Yongin si, Gyeonggi-Do, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021863397","display_name":"Insup Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Insup Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020011072","display_name":"Youngsoo Shin","orcid":"https://orcid.org/0000-0002-7474-9212"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngsoo Shin","raw_affiliation_strings":["Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2492,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.82674564,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"31","issue":"3","first_page":"391","last_page":"403"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.7552063465118408},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6506584882736206},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6503928899765015},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5571582913398743},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5016381740570068},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.44535544514656067},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4438897371292114},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.424045592546463},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4238196611404419},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25841519236564636},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.24559372663497925},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2368168830871582},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.211803138256073},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16684260964393616},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16438961029052734},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.11023297905921936}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.7552063465118408},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6506584882736206},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6503928899765015},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5571582913398743},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5016381740570068},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.44535544514656067},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4438897371292114},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.424045592546463},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4238196611404419},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25841519236564636},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.24559372663497925},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2368168830871582},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.211803138256073},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16684260964393616},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16438961029052734},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.11023297905921936},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2171963","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2171963","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1503103436","https://openalex.org/W1908393759","https://openalex.org/W1949737515","https://openalex.org/W2017370932","https://openalex.org/W2041514074","https://openalex.org/W2048984379","https://openalex.org/W2086775835","https://openalex.org/W2097059489","https://openalex.org/W2098560306","https://openalex.org/W2101829102","https://openalex.org/W2119060381","https://openalex.org/W2136446383","https://openalex.org/W2140210510","https://openalex.org/W2153087216","https://openalex.org/W2158899676","https://openalex.org/W2169033838","https://openalex.org/W2169278276","https://openalex.org/W2173072002","https://openalex.org/W3140585965","https://openalex.org/W4234463038","https://openalex.org/W4239200527","https://openalex.org/W6677925612"],"related_works":["https://openalex.org/W2061180121","https://openalex.org/W2259094912","https://openalex.org/W2546524276","https://openalex.org/W4226239708","https://openalex.org/W2152979262","https://openalex.org/W3127845477","https://openalex.org/W2005728592","https://openalex.org/W4239594101","https://openalex.org/W229101532","https://openalex.org/W2113774150"],"abstract_inverted_index":{"Active":[0],"leakage":[1,25],"is":[2,97],"transient,":[3],"which":[4],"can":[5,21],"be":[6,62,111],"suppressed":[7],"by":[8,26,118],"design":[9,93],"techniques":[10],"such":[11],"as":[12,69,71],"dual-":[13],"<i":[14],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[15],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">Vt</i>":[16],".":[17],"Active-mode":[18],"power-gating":[19,27],"(AMPG)":[20],"further":[22],"reduce":[23],"active":[24],"groups":[28],"of":[29,49,83,87,94,105,137,147],"gates":[30,50],"that":[31,36,109,142],"perform":[32],"computations":[33],"with":[34,121],"results":[35],"are":[37],"not":[38],"loaded":[39],"due":[40,100],"to":[41,61,64,77,101],"clock-gating.":[42],"AMPG":[43,89,95,138],"involves":[44],"several":[45,127],"challenges;":[46],"the":[47,81,84,102,135,140],"grouping":[48],"must":[51,110],"take":[52],"circuit":[53,72],"timing":[54],"into":[55],"account,":[56],"and":[57,152],"current":[58],"switches":[59],"need":[60],"sized":[63],"preserve":[65],"power":[66,122,148],"network":[67,123],"integrity":[68],"well":[70],"timing.":[73,153],"We":[74,114],"propose":[75],"solutions":[76],"these":[78,116],"problems":[79],"in":[80,131,139,145],"content":[82],"entire":[85],"process":[86],"synthesizing":[88],"circuits.":[90],"The":[91],"physical":[92],"circuits":[96,129,141],"also":[98],"difficult":[99],"large":[103],"number":[104],"virtual":[106],"ground":[107],"rails":[108],"mutually":[112],"isolated.":[113],"address":[115],"issues":[117],"integrating":[119],"placement":[120],"synthesis.":[124],"Experiments":[125],"on":[126],"test":[128],"implemented":[130],"45-nm":[132],"technology":[133],"demonstrate":[134],"effectiveness":[136],"we":[143],"synthesized,":[144],"terms":[146],"consumption,":[149],"area,":[150],"wirelength,":[151]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}