{"id":"https://openalex.org/W2012885622","doi":"https://doi.org/10.1109/tcad.2011.2171183","title":"Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications","display_name":"Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications","publication_year":2012,"publication_date":"2012-02-22","ids":{"openalex":"https://openalex.org/W2012885622","doi":"https://doi.org/10.1109/tcad.2011.2171183","mag":"2012885622"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2171183","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2171183","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103453947","display_name":"Sourasis Das","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sourasis Das","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India","Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076542292","display_name":"Ansuman Banerjee","orcid":"https://orcid.org/0000-0003-0220-646X"},"institutions":[{"id":"https://openalex.org/I6498739","display_name":"Indian Statistical Institute","ror":"https://ror.org/00q2w1j53","country_code":"IN","type":"education","lineage":["https://openalex.org/I6498739"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ansuman Banerjee","raw_affiliation_strings":["Advanced Computing and Microelectronics Unit, Indian Statistical Institute, Kolkata, India","Adv. Comput. & Microelectron.Unit, Indian Stat. Inst., Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Computing and Microelectronics Unit, Indian Statistical Institute, Kolkata, India","institution_ids":["https://openalex.org/I6498739"]},{"raw_affiliation_string":"Adv. Comput. & Microelectron.Unit, Indian Stat. Inst., Kolkata, India","institution_ids":["https://openalex.org/I6498739"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033329960","display_name":"Pallab Dasgupta","orcid":"https://orcid.org/0000-0002-2178-8154"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallab Dasgupta","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India","Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Dept. of Computer Science and Engg, Indian Institute of Technology Kharagpur, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3473,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61123363,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"31","issue":"3","first_page":"447","last_page":"451"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.666278600692749},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.6500332355499268},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.5176520943641663},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.47675949335098267},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4659937620162964},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.46116915345191956},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.287990927696228},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14996179938316345}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.666278600692749},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.6500332355499268},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.5176520943641663},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.47675949335098267},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4659937620162964},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.46116915345191956},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.287990927696228},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14996179938316345},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2171183","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2171183","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1495461922","https://openalex.org/W1589840570","https://openalex.org/W1889085354","https://openalex.org/W1896160926","https://openalex.org/W1976597924","https://openalex.org/W2023808162","https://openalex.org/W2096443114","https://openalex.org/W2106767029","https://openalex.org/W2116153111","https://openalex.org/W2340735175","https://openalex.org/W3150683616","https://openalex.org/W4248877409","https://openalex.org/W6629709275","https://openalex.org/W6635220215"],"related_works":["https://openalex.org/W2145025660","https://openalex.org/W2171674700","https://openalex.org/W2049993111","https://openalex.org/W1922520186","https://openalex.org/W1903167137","https://openalex.org/W1950421680","https://openalex.org/W2034589735","https://openalex.org/W2045204345","https://openalex.org/W2020416949","https://openalex.org/W1999356246"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,44],"formal":[4,10,35],"methodology":[5],"for":[6,17,20,28],"test":[7,18,46],"generation":[8,19,27],"from":[9],"specifications.":[11,55],"Our":[12],"method":[13],"can":[14],"be":[15,48],"used":[16],"critical":[21,29],"faults":[22,30],"in":[23],"component-based":[24],"designs.":[25],"Test":[26],"is":[31,72],"done":[32],"entirely":[33],"using":[34],"specifications":[36],"and":[37],"therefore":[38],"the":[39,54,69],"theory":[40,57],"inherently":[41],"guarantees":[42],"that":[43],"generated":[45],"will":[47],"applicable":[49],"to":[50],"any":[51],"implementation":[52],"of":[53,66],"The":[56],"makes":[58],"fault":[59],"analysis":[60],"possible":[61],"at":[62],"an":[63],"abstract":[64],"level":[65],"design":[67],"where":[68],"complete":[70],"logic":[71],"not":[73],"specified.":[74]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
