{"id":"https://openalex.org/W2138398184","doi":"https://doi.org/10.1109/tcad.2011.2165068","title":"An Algorithmic Study of Exact Route Matching for Integrated Circuits","display_name":"An Algorithmic Study of Exact Route Matching for Integrated Circuits","publication_year":2011,"publication_date":"2011-11-21","ids":{"openalex":"https://openalex.org/W2138398184","doi":"https://doi.org/10.1109/tcad.2011.2165068","mag":"2138398184"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2165068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2165068","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103071783","display_name":"Muhammet Mustafa \u00d6zdal","orcid":"https://orcid.org/0000-0002-6239-9622"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Muhammet Mustafa Ozdal","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087624505","display_name":"Renato Hentschke","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Renato Fernandes Hentschke","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.5325,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.72077566,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"30","issue":"12","first_page":"1842","last_page":"1855"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.7658294439315796},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7144765257835388},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.6848782896995544},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4897008240222931},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4529038369655609},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.44786447286605835},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.43972596526145935},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.43351489305496216},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4316445589065552},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3934703767299652},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.36691445112228394},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3510007858276367},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18067458271980286},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13049975037574768},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12781518697738647},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09140455722808838}],"concepts":[{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.7658294439315796},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7144765257835388},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.6848782896995544},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4897008240222931},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4529038369655609},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.44786447286605835},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.43972596526145935},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.43351489305496216},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4316445589065552},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3934703767299652},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.36691445112228394},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3510007858276367},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18067458271980286},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13049975037574768},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12781518697738647},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09140455722808838},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2165068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2165068","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1550639219","https://openalex.org/W1598536440","https://openalex.org/W1974610062","https://openalex.org/W1997134428","https://openalex.org/W2028326940","https://openalex.org/W2045697850","https://openalex.org/W2055336889","https://openalex.org/W2068409038","https://openalex.org/W2096970935","https://openalex.org/W2097066086","https://openalex.org/W2103741020","https://openalex.org/W2106928112","https://openalex.org/W2115480816","https://openalex.org/W2124525851","https://openalex.org/W2128161498","https://openalex.org/W2137890965","https://openalex.org/W2146519106","https://openalex.org/W2147555712","https://openalex.org/W2148328797","https://openalex.org/W2165465743","https://openalex.org/W2165849611","https://openalex.org/W2295318563","https://openalex.org/W3145069811","https://openalex.org/W3145225676","https://openalex.org/W3148657002","https://openalex.org/W3149999751","https://openalex.org/W4237638069","https://openalex.org/W4243621528","https://openalex.org/W4245484162","https://openalex.org/W4248699322","https://openalex.org/W6657784182","https://openalex.org/W6679151251"],"related_works":["https://openalex.org/W2171793444","https://openalex.org/W2743305891","https://openalex.org/W3173072440","https://openalex.org/W2161355881","https://openalex.org/W2051886008","https://openalex.org/W4235818534","https://openalex.org/W3000171651","https://openalex.org/W4223903705","https://openalex.org/W1999810416","https://openalex.org/W2165817382"],"abstract_inverted_index":{"As":[0],"system-on-chip":[1],"designs":[2],"are":[3],"getting":[4],"more":[5],"popular,":[6],"the":[7,25,45,60,83,102],"importance":[8],"of":[9,27,47,104],"design":[10,36],"automation":[11],"for":[12,44],"analog":[13,42],"and":[14,74,77],"mixed-signal":[15],"integrated":[16],"circuits":[17],"is":[18,32],"increasing.":[19],"In":[20],"this":[21,67,96],"paper,":[22],"we":[23,52,69],"study":[24],"problem":[26,63],"exact":[28],"route":[29,61,85],"matching,":[30],"which":[31],"an":[33],"important":[34,71],"physical":[35],"constraint":[37],"commonly":[38],"imposed":[39],"on":[40,66],"specific":[41],"signals":[43],"purpose":[46],"correct":[48],"functionality.":[49],"For":[50],"this,":[51],"first":[53],"propose":[54,75],"a":[55],"mathematical":[56],"formulation":[57],"that":[58],"models":[59],"matching":[62,86],"exactly.":[64],"Based":[65],"formulation,":[68],"derive":[70],"theoretical":[72],"conclusions,":[73],"dynamic-programming":[76],"heuristic":[78],"search":[79],"algorithms":[80],"to":[81,95],"solve":[82],"min-cost":[84],"problem.":[87,97],"We":[88],"also":[89],"discuss":[90],"various":[91],"practical":[92],"considerations":[93],"related":[94],"Our":[98],"experimental":[99],"results":[100],"show":[101],"effectiveness":[103],"our":[105],"algorithms.":[106]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
