{"id":"https://openalex.org/W2096123149","doi":"https://doi.org/10.1109/tcad.2011.2163159","title":"Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects","display_name":"Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects","publication_year":2011,"publication_date":"2011-11-21","ids":{"openalex":"https://openalex.org/W2096123149","doi":"https://doi.org/10.1109/tcad.2011.2163159","mag":"2096123149"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2163159","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2163159","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002029078","display_name":"Junxia Ma","orcid":"https://orcid.org/0000-0002-0151-3188"},"institutions":[{"id":"https://openalex.org/I4210119403","display_name":"LSI Solutions (United States)","ror":"https://ror.org/02st8gf30","country_code":"US","type":"company","lineage":["https://openalex.org/I4210119403"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Junxia Ma","raw_affiliation_strings":["LSI Corporation, Milpitas, CA, USA","LSI Corp., Milpitas, CA, USA"],"affiliations":[{"raw_affiliation_string":"LSI Corporation, Milpitas, CA, USA","institution_ids":[]},{"raw_affiliation_string":"LSI Corp., Milpitas, CA, USA","institution_ids":["https://openalex.org/I4210119403"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113697198","display_name":"Mohammad Tehranipoor","orcid":null},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammad Tehranipoor","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA","Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA#TAB#","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5002029078"],"corresponding_institution_ids":["https://openalex.org/I4210119403"],"apc_list":null,"apc_paid":null,"fwci":2.5186,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.90006681,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"30","issue":"12","first_page":"1923","last_page":"1934"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5706547498703003},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.570337176322937},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.549697995185852},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.527677595615387},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5196610689163208},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.518807590007782},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.4997098445892334},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4732314348220825},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.46727004647254944},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4503062665462494},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4488518536090851},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4273386001586914},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.42436307668685913},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.39170336723327637},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30645912885665894},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26823869347572327},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1749383509159088},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.10509756207466125},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09036970138549805},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07232934236526489}],"concepts":[{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5706547498703003},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.570337176322937},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.549697995185852},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.527677595615387},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5196610689163208},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.518807590007782},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.4997098445892334},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4732314348220825},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.46727004647254944},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4503062665462494},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4488518536090851},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4273386001586914},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.42436307668685913},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.39170336723327637},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30645912885665894},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26823869347572327},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1749383509159088},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.10509756207466125},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09036970138549805},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07232934236526489},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2163159","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2163159","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1557977552","https://openalex.org/W1568407911","https://openalex.org/W1606206944","https://openalex.org/W1788608581","https://openalex.org/W1843801354","https://openalex.org/W1966348745","https://openalex.org/W1966741973","https://openalex.org/W1980499623","https://openalex.org/W2001352955","https://openalex.org/W2018607921","https://openalex.org/W2028350975","https://openalex.org/W2054718237","https://openalex.org/W2075400577","https://openalex.org/W2104295613","https://openalex.org/W2106006800","https://openalex.org/W2107236168","https://openalex.org/W2109791184","https://openalex.org/W2119691242","https://openalex.org/W2129428181","https://openalex.org/W2134509461","https://openalex.org/W2134980804","https://openalex.org/W2136680550","https://openalex.org/W2148008037","https://openalex.org/W2149998114","https://openalex.org/W2151594754","https://openalex.org/W2156749158","https://openalex.org/W2160055399","https://openalex.org/W2163262735","https://openalex.org/W2171236961","https://openalex.org/W3145605605","https://openalex.org/W4233794767","https://openalex.org/W4236133696","https://openalex.org/W4256630426","https://openalex.org/W6675809723","https://openalex.org/W6679827605","https://openalex.org/W6680321542","https://openalex.org/W6680497249","https://openalex.org/W6685440189"],"related_works":["https://openalex.org/W2596661993","https://openalex.org/W2367268051","https://openalex.org/W2132496963","https://openalex.org/W2533759086","https://openalex.org/W2094215088","https://openalex.org/W4237760093","https://openalex.org/W2811251486","https://openalex.org/W1973159305","https://openalex.org/W2025876240","https://openalex.org/W1989947234"],"abstract_inverted_index":{"As":[0,20],"technology":[1],"shrinks,":[2],"gate":[3],"sensitivity":[4],"to":[5,9,43,53,57,66,86],"noise":[6,25,47],"increases":[7,134],"due":[8],"supply":[10,24,45],"voltage":[11,18,46,98,145],"scaling":[12,15],"and":[13,35,60,70,104,119,142],"limited":[14],"of":[16,72,96],"the":[17,68,73,94,110,137,151,164],"threshold.":[19],"a":[21,28,78],"result,":[22],"power":[23],"(PSN)":[26],"plays":[27],"greater":[29],"role":[30],"in":[31,156,174],"sub-100":[32],"nm":[33],"technologies":[34],"creates":[36],"signal":[37],"integrity":[38],"issues.":[39],"It":[40],"is":[41,84,107,131,172],"vital":[42],"consider":[44],"effects:":[48],"1)":[49],"during":[50,62],"design":[51],"validation":[52,105,169],"apply":[54],"sufficient":[55],"guardbands":[56],"critical":[58,91,140,152],"paths,":[59,141],"2)":[61],"path":[63,158],"delay":[64],"test":[65],"ensure":[67],"performance":[69],"reliability":[71],"chip.":[74],"In":[75],"this":[76],"paper,":[77],"novel":[79],"layout-aware":[80],"pattern":[81,102,168],"generation":[82,103],"procedure":[83],"proposed":[85,101,129,161],"maximize":[87],"PSN":[88],"effects":[89],"on":[90,109,147,150],"paths":[92,153],"considering":[93],"impact":[95],"local":[97],"drop.":[99],"The":[100,160],"flow":[106],"implemented":[108],"ITC'99":[111],"b19":[112],"benchmark.":[113],"Experimental":[114],"results":[115,155],"for":[116],"both":[117],"wire-bond":[118],"flip-chip":[120],"packaging":[121],"styles":[122],"are":[123],"presented.":[124],"Results":[125],"demonstrate":[126],"that":[127,171],"our":[128],"method":[130,162],"fast,":[132],"significantly":[133],"switching":[135],"around":[136],"functionally":[138],"testable":[139],"induces":[143],"large":[144],"drop":[146],"cells":[148],"placed":[149],"which":[154],"increased":[157],"delay.":[159],"eliminates":[163],"very":[165],"time":[166],"consuming":[167],"phase":[170],"practised":[173],"industry.":[175]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}