{"id":"https://openalex.org/W2141400030","doi":"https://doi.org/10.1109/tcad.2011.2160174","title":"Memory Built-in Self-Repair Planning Framework for RAMs in SoCs","display_name":"Memory Built-in Self-Repair Planning Framework for RAMs in SoCs","publication_year":2011,"publication_date":"2011-10-18","ids":{"openalex":"https://openalex.org/W2141400030","doi":"https://doi.org/10.1109/tcad.2011.2160174","mag":"2141400030"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2160174","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2160174","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081576356","display_name":"Chih-Sheng Hou","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Sheng Hou","raw_affiliation_strings":["Advanced Reliable Systems Laboratory, Department of Electrical Engineering, National Central University, Jhong Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Reliable Systems Laboratory, Department of Electrical Engineering, National Central University, Jhong Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100741020","display_name":"Jin-Fu Li","orcid":"https://orcid.org/0000-0003-1961-9674"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jin-Fu Li","raw_affiliation_strings":["Advanced Reliable Systems Laboratory, Department of Electrical Engineering, National Central University, Jhong Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Reliable Systems Laboratory, Department of Electrical Engineering, National Central University, Jhong Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jhongli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109234824","display_name":"Tsu-Wei Tseng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tsu-Wei Tseng","raw_affiliation_strings":["Information and Communications Research Laboratory, Industrial Technology Research Institute, Hsinchu, Taiwan","Inf. & Commun. Res. Lab, Ind. Technol. Res. Inst., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information and Communications Research Laboratory, Industrial Technology Research Institute, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]},{"raw_affiliation_string":"Inf. & Commun. Res. Lab, Ind. Technol. Res. Inst., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2646,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.81880712,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"30","issue":"11","first_page":"1731","last_page":"1743"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9900000095367432,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.5725666284561157},{"id":"https://openalex.org/keywords/test-plan","display_name":"Test plan","score":0.5247355103492737},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41353151202201843},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3433464765548706},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3200191259384155},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2793002724647522},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.09100401401519775}],"concepts":[{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.5725666284561157},{"id":"https://openalex.org/C12148698","wikidata":"https://www.wikidata.org/wiki/Q364651","display_name":"Test plan","level":3,"score":0.5247355103492737},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41353151202201843},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3433464765548706},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3200191259384155},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2793002724647522},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.09100401401519775},{"id":"https://openalex.org/C173291955","wikidata":"https://www.wikidata.org/wiki/Q732332","display_name":"Weibull distribution","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2160174","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2160174","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1563309336","https://openalex.org/W1792362277","https://openalex.org/W1922918362","https://openalex.org/W1973508428","https://openalex.org/W1974850953","https://openalex.org/W1976009011","https://openalex.org/W2005160252","https://openalex.org/W2007364715","https://openalex.org/W2030989963","https://openalex.org/W2038176281","https://openalex.org/W2040066907","https://openalex.org/W2060071452","https://openalex.org/W2079486027","https://openalex.org/W2096314285","https://openalex.org/W2100312232","https://openalex.org/W2102136494","https://openalex.org/W2114185924","https://openalex.org/W2114930002","https://openalex.org/W2115013189","https://openalex.org/W2116273964","https://openalex.org/W2119482888","https://openalex.org/W2121938580","https://openalex.org/W2122979515","https://openalex.org/W2124479423","https://openalex.org/W2129780639","https://openalex.org/W2132635813","https://openalex.org/W2134822007","https://openalex.org/W2135524973","https://openalex.org/W2137795611","https://openalex.org/W2138246797","https://openalex.org/W2149233130","https://openalex.org/W2155640457","https://openalex.org/W2157130998","https://openalex.org/W2171372273","https://openalex.org/W3142145731","https://openalex.org/W4256298596","https://openalex.org/W6674675842","https://openalex.org/W6675581240","https://openalex.org/W6677639902","https://openalex.org/W6677993950","https://openalex.org/W6678212036","https://openalex.org/W6679523228","https://openalex.org/W6679819986"],"related_works":["https://openalex.org/W2036806516","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W2142443274","https://openalex.org/W13556768","https://openalex.org/W2912613323","https://openalex.org/W2100663632","https://openalex.org/W2068239131","https://openalex.org/W2353292666"],"abstract_inverted_index":{"Built-in":[0],"self-repair":[1],"(BISR)":[2],"techniques":[3,39],"are":[4,46],"widely":[5],"used":[6,88],"to":[7,89,113],"enhance":[8],"the":[9,60,91,100,119,122,125,137,143,147,162,167],"yield":[10],"of":[11,23,25,68,94,102,124,127],"random":[12],"access":[13],"memories":[14],"(RAMs)":[15],"in":[16,34,62,96,149,185],"a":[17,35,53,69,79,83,97,106,150,188,196],"system-on-chip":[18],"(SoC)":[19],"which":[20,76],"typically":[21],"consists":[22,67],"hundreds":[24],"RAMs.":[26],"Hence,":[27],"many":[28],"BISR":[29,43,55,80,107,116,144,163,190,198],"circuits":[30,44],"may":[31],"be":[32,159],"needed":[33],"such":[36],"SoC.":[37,151],"Effective":[38],"for":[40,59,73,118,146,171],"planning":[41,56],"these":[42],"thus":[45],"imperative.":[47],"In":[48],"this":[49],"paper,":[50],"we":[51],"propose":[52],"memory":[54,70,128],"(MBiP)":[57],"framework":[58,66,170],"RAMs":[61,75,95,120,148,173],"SoCs.":[63],"The":[64],"MBiP":[65,139,169],"grouping":[71,129],"algorithm":[72,86,110],"selecting":[74],"can":[77,140,158],"share":[78],"circuit.":[81],"Then,":[82],"test":[84,92,103,131,182],"scheduling":[85],"is":[87,111],"determine":[90],"sequence":[93],"SoC":[98],"under":[99,121,174],"constraint":[101,178,184],"power.":[104],"Finally,":[105],"scheme":[108,191],"allocation":[109],"proposed":[112,138,168],"allocate":[114],"different":[115],"schemes":[117,145,164],"constraints":[123],"results":[126,134],"and":[130,179],"scheduling.":[132],"Simulation":[133],"show":[135],"that":[136],"effectively":[141],"plan":[142],"For":[152],"example,":[153],"about":[154],"22%":[155],"area":[156],"reduction":[157],"achieved":[160],"by":[161,166],"planned":[165],"50":[172],"1.5":[175],"mm":[176],"distance":[177],"350":[180],"mW":[181],"power":[183],"comparison":[186],"with":[187],"dedicated":[189],"(i.e.,":[192],"each":[193],"RAM":[194],"has":[195],"self-contained":[197],"circuit).":[199]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
