{"id":"https://openalex.org/W2166029537","doi":"https://doi.org/10.1109/tcad.2011.2110592","title":"High-Level Synthesis for FPGAs: From Prototyping to Deployment","display_name":"High-Level Synthesis for FPGAs: From Prototyping to Deployment","publication_year":2011,"publication_date":"2011-03-22","ids":{"openalex":"https://openalex.org/W2166029537","doi":"https://doi.org/10.1109/tcad.2011.2110592","mag":"2166029537"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2110592","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2110592","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016776689","display_name":"Jason Cong","orcid":"https://orcid.org/0000-0003-2887-6963"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jason Cong","raw_affiliation_strings":["University of California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100682338","display_name":"Bin Liu","orcid":"https://orcid.org/0000-0002-5836-2333"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bin Liu","raw_affiliation_strings":["University of California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014827775","display_name":"Stephen Neuendorffer","orcid":"https://orcid.org/0000-0003-2956-8428"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Neuendorffer","raw_affiliation_strings":["Research Laboratories, Xilinx, Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Research Laboratories, Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111611510","display_name":"Juanjo Noguera","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Juanjo Noguera","raw_affiliation_strings":["Research Laboratories, Xilinx, Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Research Laboratories, Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011464762","display_name":"Kees Vissers","orcid":"https://orcid.org/0000-0002-6249-315X"},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kees Vissers","raw_affiliation_strings":["Research Laboratories, Xilinx, Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Research Laboratories, Xilinx, Inc., San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037210004","display_name":"Zhiru Zhang","orcid":"https://orcid.org/0000-0002-0778-0308"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhiru Zhang","raw_affiliation_strings":["Auto ESL Design Technologies, Inc., Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Auto ESL Design Technologies, Inc., Los Angeles, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5016776689"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":41.2298,"has_fulltext":false,"cited_by_count":832,"citation_normalized_percentile":{"value":0.99926342,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":"30","issue":"4","first_page":"473","last_page":"491"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8487339019775391},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7552275061607361},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6479507088661194},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6360039114952087},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.5257350206375122},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.46798205375671387},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4599967896938324},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.44115614891052246},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16831687092781067},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1210019588470459}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8487339019775391},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7552275061607361},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6479507088661194},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6360039114952087},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.5257350206375122},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.46798205375671387},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4599967896938324},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.44115614891052246},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16831687092781067},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1210019588470459},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2011.2110592","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2110592","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.228.6866","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.228.6866","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ballade.cs.ucla.edu/%7Econg/papers/j-83.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.5,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":116,"referenced_works":["https://openalex.org/W25231633","https://openalex.org/W25598901","https://openalex.org/W42313609","https://openalex.org/W83586921","https://openalex.org/W200320269","https://openalex.org/W1494930385","https://openalex.org/W1498455513","https://openalex.org/W1500906976","https://openalex.org/W1522612633","https://openalex.org/W1536710422","https://openalex.org/W1543657314","https://openalex.org/W1548598239","https://openalex.org/W1577039630","https://openalex.org/W1593855808","https://openalex.org/W1597755753","https://openalex.org/W1604677972","https://openalex.org/W1965864973","https://openalex.org/W1966415715","https://openalex.org/W1977034714","https://openalex.org/W1982205631","https://openalex.org/W1986207994","https://openalex.org/W1989435461","https://openalex.org/W1994126939","https://openalex.org/W2003446039","https://openalex.org/W2003631319","https://openalex.org/W2004144979","https://openalex.org/W2011784906","https://openalex.org/W2024612992","https://openalex.org/W2028749987","https://openalex.org/W2029709974","https://openalex.org/W2036779190","https://openalex.org/W2042202727","https://openalex.org/W2051679558","https://openalex.org/W2053013213","https://openalex.org/W2057108708","https://openalex.org/W2063477863","https://openalex.org/W2068528206","https://openalex.org/W2074537610","https://openalex.org/W2075655993","https://openalex.org/W2078043527","https://openalex.org/W2081494357","https://openalex.org/W2082085231","https://openalex.org/W2083831409","https://openalex.org/W2086178110","https://openalex.org/W2091158003","https://openalex.org/W2091636254","https://openalex.org/W2091819707","https://openalex.org/W2093842169","https://openalex.org/W2096525649","https://openalex.org/W2099012357","https://openalex.org/W2100882463","https://openalex.org/W2101811680","https://openalex.org/W2102562397","https://openalex.org/W2103625331","https://openalex.org/W2106574988","https://openalex.org/W2108089272","https://openalex.org/W2110085199","https://openalex.org/W2110425399","https://openalex.org/W2112432448","https://openalex.org/W2113085705","https://openalex.org/W2113308450","https://openalex.org/W2113745543","https://openalex.org/W2114266730","https://openalex.org/W2118229154","https://openalex.org/W2123173853","https://openalex.org/W2127699991","https://openalex.org/W2129174252","https://openalex.org/W2131023841","https://openalex.org/W2131065168","https://openalex.org/W2136291591","https://openalex.org/W2139709520","https://openalex.org/W2141597697","https://openalex.org/W2142252430","https://openalex.org/W2145601734","https://openalex.org/W2147088458","https://openalex.org/W2147293397","https://openalex.org/W2150188692","https://openalex.org/W2151415616","https://openalex.org/W2153185479","https://openalex.org/W2153801278","https://openalex.org/W2156420848","https://openalex.org/W2157976860","https://openalex.org/W2159414285","https://openalex.org/W2164287116","https://openalex.org/W2165689945","https://openalex.org/W2167220901","https://openalex.org/W2170049777","https://openalex.org/W2181438886","https://openalex.org/W2191327475","https://openalex.org/W2293374899","https://openalex.org/W2478551317","https://openalex.org/W2481725867","https://openalex.org/W2482246557","https://openalex.org/W3144368627","https://openalex.org/W3144599787","https://openalex.org/W3148913902","https://openalex.org/W4206153422","https://openalex.org/W4211008702","https://openalex.org/W4230104651","https://openalex.org/W4231345919","https://openalex.org/W4231413003","https://openalex.org/W4231990911","https://openalex.org/W4232714327","https://openalex.org/W4242881570","https://openalex.org/W4246166885","https://openalex.org/W4250438344","https://openalex.org/W4250936748","https://openalex.org/W4252239987","https://openalex.org/W4253289325","https://openalex.org/W4255135910","https://openalex.org/W6601038207","https://openalex.org/W6635964534","https://openalex.org/W6666449423","https://openalex.org/W6681482952","https://openalex.org/W6684288923","https://openalex.org/W6685825094"],"related_works":["https://openalex.org/W2998132311","https://openalex.org/W2164041287","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2406926880","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309","https://openalex.org/W272033699","https://openalex.org/W1692883217"],"abstract_inverted_index":{"Escalating":[0],"system-on-chip":[1],"design":[2,7,43,164],"complexity":[3],"is":[4,45],"pushing":[5],"the":[6,11,20,35,108,142,150],"community":[8],"to":[9,40,106,167],"raise":[10],"level":[12],"of":[13,23,26,58,110,133],"abstraction":[14],"beyond":[15],"register":[16],"transfer":[17],"level.":[18],"Despite":[19],"unsuccessful":[21],"adoptions":[22],"early":[24],"generations":[25],"commercial":[27],"high-level":[28],"synthesis":[29,113],"(HLS)":[30],"systems,":[31],"we":[32,88],"believe":[33],"that":[34,149],"tipping":[36],"point":[37],"for":[38,49],"transitioning":[39],"HLS":[41,59,79,92,134,151],"msystem-on-chip":[42],"complexityethodology":[44],"happening":[46],"now,":[47],"especially":[48],"field-programmable":[50],"gate":[51],"array":[52],"(FPGA)":[53],"designs.":[54,139],"The":[55],"latest":[56],"generation":[57],"tools":[60],"has":[61],"made":[62],"significant":[63],"progress":[64],"in":[65,77,158],"providing":[66],"wide":[67],"language":[68],"coverage":[69],"and":[70,81],"robust":[71],"compilation":[72],"technology,":[73],"platform-based":[74],"modeling,":[75],"advancement":[76],"core":[78],"algorithms,":[80],"a":[82,145],"domain-specific":[83,96],"approach.":[84],"In":[85,140],"this":[86],"paper,":[87],"use":[89],"AutoESL's":[90],"AutoPilot":[91],"tool":[93],"coupled":[94],"with":[95,162],"system-level":[97],"implementation":[98],"platforms":[99],"developed":[100],"by":[101],"Xilinx":[102,123],"as":[103,128],"an":[104,155],"example":[105],"demonstrate":[107],"effectiveness":[109],"state-of-art":[111],"C-to-FPGA":[112],"solutions":[114,135],"targeting":[115,122],"multiple":[116],"application":[117],"domains.":[118],"Complex":[119],"industrial":[120],"designs":[121],"FPGAs":[124],"are":[125],"also":[126],"presented":[127],"case":[129],"studies,":[130],"including":[131],"comparison":[132],"versus":[136],"optimized":[137],"manual":[138],"particular,":[141],"experiment":[143],"on":[144],"sphere":[146],"decoder":[147],"shows":[148],"solution":[152],"can":[153],"achieve":[154],"11-31%":[156],"reduction":[157],"FPGA":[159],"resource":[160],"usage":[161],"improved":[163],"productivity":[165],"compared":[166],"hand-coded":[168],"design.":[169]},"counts_by_year":[{"year":2026,"cited_by_count":6},{"year":2025,"cited_by_count":46},{"year":2024,"cited_by_count":46},{"year":2023,"cited_by_count":66},{"year":2022,"cited_by_count":61},{"year":2021,"cited_by_count":52},{"year":2020,"cited_by_count":66},{"year":2019,"cited_by_count":60},{"year":2018,"cited_by_count":60},{"year":2017,"cited_by_count":68},{"year":2016,"cited_by_count":79},{"year":2015,"cited_by_count":61},{"year":2014,"cited_by_count":51},{"year":2013,"cited_by_count":66},{"year":2012,"cited_by_count":37}],"updated_date":"2026-04-11T08:14:18.477133","created_date":"2025-10-10T00:00:00"}