{"id":"https://openalex.org/W2151942105","doi":"https://doi.org/10.1109/tcad.2011.2106851","title":"SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs","display_name":"SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs","publication_year":2011,"publication_date":"2011-05-17","ids":{"openalex":"https://openalex.org/W2151942105","doi":"https://doi.org/10.1109/tcad.2011.2106851","mag":"2151942105"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2011.2106851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2106851","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110430876","display_name":"Shahin Golshan","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shahin Golshan","raw_affiliation_strings":["Department of Computer Sciences, University of California, Irvine, Irvine, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, University of California, Irvine, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043632585","display_name":"Hessam Kooti","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hessam Kooti","raw_affiliation_strings":["Department of Computer Sciences, University of California, Irvine, Irvine, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, University of California, Irvine, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111951877","display_name":"Elaheh Bozorgzadeh","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elaheh Bozorgzadeh","raw_affiliation_strings":["Department of Computer Sciences, University of California, Irvine, Irvine, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, University of California, Irvine, Irvine, CA, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110430876"],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":null,"apc_paid":null,"fwci":0.7949,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.77177089,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"30","issue":"6","first_page":"829","last_page":"840"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.8916581273078918},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6837142705917358},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6124642491340637},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6077895760536194},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5674766898155212},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5598233342170715},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5416801571846008},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.5246646404266357},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45782551169395447},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.43944263458251953},{"id":"https://openalex.org/keywords/replica","display_name":"Replica","score":0.42452847957611084},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23661494255065918},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14013779163360596},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11070272326469421},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10848164558410645}],"concepts":[{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.8916581273078918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6837142705917358},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6124642491340637},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6077895760536194},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5674766898155212},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5598233342170715},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5416801571846008},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.5246646404266357},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45782551169395447},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.43944263458251953},{"id":"https://openalex.org/C2775937380","wikidata":"https://www.wikidata.org/wiki/Q1232589","display_name":"Replica","level":2,"score":0.42452847957611084},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23661494255065918},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14013779163360596},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11070272326469421},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10848164558410645},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2011.2106851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2011.2106851","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W819047989","https://openalex.org/W1523051745","https://openalex.org/W1573000522","https://openalex.org/W1625650886","https://openalex.org/W1970885193","https://openalex.org/W2015598675","https://openalex.org/W2064559570","https://openalex.org/W2114151714","https://openalex.org/W2114772983","https://openalex.org/W2115299214","https://openalex.org/W2129183345","https://openalex.org/W2130489211","https://openalex.org/W2131044255","https://openalex.org/W2135743241","https://openalex.org/W2143474538","https://openalex.org/W2161815502","https://openalex.org/W2169480831","https://openalex.org/W2182039723","https://openalex.org/W3142488006","https://openalex.org/W3151322387","https://openalex.org/W4251792943","https://openalex.org/W6636463469","https://openalex.org/W6666544085"],"related_works":["https://openalex.org/W3136752381","https://openalex.org/W1994477182","https://openalex.org/W2354337233","https://openalex.org/W3194108321","https://openalex.org/W1749592617","https://openalex.org/W2770296460","https://openalex.org/W2964411820","https://openalex.org/W2776397918","https://openalex.org/W634025176","https://openalex.org/W2160017847"],"abstract_inverted_index":{"Although":[0],"triple":[1],"modular":[2,74],"redundancy":[3,75],"(TMR)":[4],"has":[5],"been":[6],"widely":[7],"used":[8],"to":[9,59,148,157,165],"mitigate":[10,60],"single":[11,98],"event":[12],"upsets":[13],"(SEUs)":[14],"in":[15,57,65,112,126,141,151,161,172,191],"static":[16],"random":[17],"access":[18],"memory-based":[19],"field-programmable":[20],"gate":[21],"arrays":[22],"(FPGAs),":[23],"SEU-caused":[24],"bridging":[25,108,132],"faults":[26,95,109,133],"between":[27],"the":[28,34,61,66,71,82,86,104,127,142,153,158,162,166,174,179,194],"triplicated":[29],"modules":[30],"do":[31],"not":[32],"guarantee":[33],"correctness":[35],"of":[36,63,73,88,93,100,106,129,169,181,193],"TMR":[37,171],"designs":[38,90],"under":[39],"all":[40],"SEUs.":[41],"In":[42],"this":[43],"paper,":[44],"we":[45,186],"present":[46],"a":[47,97],"novel":[48],"computer-aided":[49],"design":[50],"flow":[51],"for":[52],"redundancy-based":[53,89],"applications":[54],"on":[55,120],"FPGAs":[56],"order":[58],"impact":[62,105],"SEUs":[64],"configuration":[67],"bitstreams.":[68],"We":[69],"introduce":[70],"notions":[72],"conflicts":[76,79],"and":[77,144],"vulnerability-gap":[78],"which":[80,152,173],"maintain":[81],"fundamental":[83],"assumption":[84],"underlying":[85],"integrity":[87],"(i.e.,":[91],"self-containment":[92],"SEU-induced":[94,107,131],"within":[96],"replica":[99],"redundant":[101],"resources).":[102],"When":[103],"is":[110],"considered":[111],"high-level":[113],"synthesis":[114],"as":[115,117,137,139],"well":[116,138],"physical":[118],"synthesis,":[119],"average":[121],"more":[122],"than":[123],"30%":[124],"improvement":[125,190],"number":[128],"potential":[130],"can":[134],"be":[135],"reached":[136],"improvements":[140],"performance":[143],"area":[145],"utilization,":[146],"compared":[147],"post-synthesis":[149,170],"TMR,":[150],"voters":[154,175],"are":[155,176],"applied":[156,177],"feedback":[159],"structures":[160],"circuit.":[163],"Compared":[164],"extreme":[167],"case":[168],"at":[178],"end":[180],"every":[182],"configurable":[183],"logic":[184],"block,":[185],"reach":[187],"38%":[188],"(26%)":[189],"performance(area)":[192],"implemented":[195],"circuits.":[196]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}