{"id":"https://openalex.org/W4253624775","doi":"https://doi.org/10.1109/tcad.2010.2092510","title":"Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains","display_name":"Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains","publication_year":2011,"publication_date":"2011-02-18","ids":{"openalex":"https://openalex.org/W4253624775","doi":"https://doi.org/10.1109/tcad.2010.2092510"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2092510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2092510","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111982449","display_name":"Shianling Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shianling Wu","raw_affiliation_strings":["Department of Creative Informatics, Kyushu Institute of Technology, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Creative Informatics, Kyushu Institute of Technology, Fukuoka, Japan","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109249989","display_name":"Laung\u2010Terng Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Laung-Terng Wang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084697545","display_name":"Xiaoqing Wen","orcid":"https://orcid.org/0000-0001-8305-604X"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Xiaoqing Wen","raw_affiliation_strings":["Department of Creative Informatics, Kyushu Institute of Technology, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Creative Informatics, Kyushu Institute of Technology, Fukuoka, Japan","institution_ids":["https://openalex.org/I207014233"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101827322","display_name":"Zhigang Jiang","orcid":"https://orcid.org/0000-0002-2574-0086"},"institutions":[{"id":"https://openalex.org/I4210107885","display_name":"Syntek Technologies (United States)","ror":"https://ror.org/01rpq5x59","country_code":"US","type":"company","lineage":["https://openalex.org/I4210107885"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhigang Jiang","raw_affiliation_strings":["SynTest Technologies, Inc., Sunnyvale, CA, USA"],"affiliations":[{"raw_affiliation_string":"SynTest Technologies, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210107885"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004041506","display_name":"Lang Tan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lang Tan","raw_affiliation_strings":["SynTest Technologies, Inc., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"SynTest Technologies, Inc., Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100433508","display_name":"Yu Zhang","orcid":"https://orcid.org/0000-0002-2052-2231"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yu Zhang","raw_affiliation_strings":["SynTest Technologies, Inc., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"SynTest Technologies, Inc., Shanghai, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032300713","display_name":"Yu Hu","orcid":"https://orcid.org/0000-0001-7906-6640"},"institutions":[{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yu Hu","raw_affiliation_strings":["Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210090176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110090558","display_name":"Wen-Ben Jone","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wen-Ben Jone","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108516165","display_name":"Michael S. Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael S. Hsiao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Polytechnic Institute, Blacksburg, VA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Polytechnic Institute, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017361488","display_name":"James Chien-Mo Li","orcid":"https://orcid.org/0000-0002-4393-5186"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"James Chien-Mo Li","raw_affiliation_strings":["Department of Electrical Engineering, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100883521","display_name":"Jiun-Lang Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jiun-Lang Huang","raw_affiliation_strings":["Department of Electrical Engineering, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101015590","display_name":"Lizhen Yu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lizhen Yu","raw_affiliation_strings":["SynTest Technologies, Inc., Shanghai, China"],"affiliations":[{"raw_affiliation_string":"SynTest Technologies, Inc., Shanghai, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":4,"institutions_distinct_count":12,"corresponding_author_ids":["https://openalex.org/A5111982449"],"corresponding_institution_ids":["https://openalex.org/I207014233"],"apc_list":null,"apc_paid":null,"fwci":0.5135,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.71340453,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"30","issue":"3","first_page":"455","last_page":"463"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.988099992275238,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8562418222427368},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7763046622276306},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.6552020311355591},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6075599193572998},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.48577454686164856},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.42405208945274353},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4187113046646118},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39713054895401},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37597158551216125},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3692966401576996},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3473498821258545},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2395942509174347},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19646510481834412},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1858595907688141},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10161527991294861},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.08613693714141846},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07583624124526978}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8562418222427368},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7763046622276306},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.6552020311355591},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6075599193572998},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.48577454686164856},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.42405208945274353},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4187113046646118},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39713054895401},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37597158551216125},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3692966401576996},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3473498821258545},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2395942509174347},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19646510481834412},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1858595907688141},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10161527991294861},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.08613693714141846},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07583624124526978},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2010.2092510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2092510","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.721.4230","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.721.4230","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.carch.ac.cn/%7Erdrg/files/Wu_TCAD2011.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5699999928474426}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332222","display_name":"University of Illinois at Urbana-Champaign","ror":"https://ror.org/047426m28"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1503570386","https://openalex.org/W1595368737","https://openalex.org/W1905213452","https://openalex.org/W2096146619","https://openalex.org/W2112187634","https://openalex.org/W2112705672","https://openalex.org/W2118744758","https://openalex.org/W2123145598","https://openalex.org/W2125424164","https://openalex.org/W2139377754","https://openalex.org/W2140842616","https://openalex.org/W2142655319","https://openalex.org/W2144817027","https://openalex.org/W2148184408","https://openalex.org/W2148271311","https://openalex.org/W2150534321","https://openalex.org/W2169632679","https://openalex.org/W4240724929","https://openalex.org/W4246686973","https://openalex.org/W4302458519","https://openalex.org/W6676710984","https://openalex.org/W6677856072"],"related_works":["https://openalex.org/W2118952760","https://openalex.org/W2075356617","https://openalex.org/W2274367941","https://openalex.org/W2390529848","https://openalex.org/W2763030692","https://openalex.org/W2553035740","https://openalex.org/W2073042086","https://openalex.org/W1974621628","https://openalex.org/W3088373974","https://openalex.org/W2789575913"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,29,100,106,110],"hybrid":[4,64],"automatic":[5],"test":[6,42,60,70],"pattern":[7,71,123],"generation":[8],"(ATPG)":[9],"technique":[10,65],"using":[11,105],"the":[12,20,37,50,83,122,138,150],"staggered":[13,38],"launch-on":[14],"capture":[15,111],"(LOC)":[16],"scheme":[17,23,39,52,153],"followed":[18],"by":[19,132,143],"one-hot":[21,51,151],"LOC":[22,113],"for":[24,77,125],"testing":[25],"delay":[26],"faults":[27],"in":[28],"scan":[30,79,84],"design":[31,85],"containing":[32],"asynchronous":[33],"clock":[34,89,95,101],"domains.":[35],"Typically,":[36],"produces":[40],"small":[41],"sets":[43],"but":[44,57],"needs":[45],"long":[46],"ATPG":[47,55,75,139],"runtime,":[48],"whereas":[49],"takes":[53],"short":[54],"runtime":[56,76,140],"yields":[58],"large":[59,127],"sets.":[61],"The":[62],"proposed":[63],"is":[66,97],"intended":[67],"to":[68,135,145,149],"reduce":[69],"count":[72],"with":[73],"acceptable":[74],"multi-million-gate":[78],"designs.":[80],"In":[81],"case":[82],"contains":[86],"multiple":[87],"synchronous":[88,94],"domains,":[90],"each":[91],"group":[92,102],"of":[93],"domains":[96],"treated":[98],"as":[99],"and":[103],"tested":[104],"launch":[107],"aligned":[108,112],"or":[109],"scheme.":[114],"By":[115],"combining":[116],"these":[117],"schemes":[118],"together,":[119],"we":[120],"found":[121],"counts":[124],"two":[126],"industrial":[128],"designs":[129],"were":[130],"reduced":[131],"approximately":[133],"1.1X":[134],"2.1X,":[136],"while":[137],"was":[141],"increased":[142],"10%":[144],"50%,":[146],"when":[147],"compared":[148],"clocking":[152],"alone.":[154]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}