{"id":"https://openalex.org/W2118498286","doi":"https://doi.org/10.1109/tcad.2010.2089569","title":"Simultaneous Technology Mapping and Placement for Delay Minimization","display_name":"Simultaneous Technology Mapping and Placement for Delay Minimization","publication_year":2011,"publication_date":"2011-02-18","ids":{"openalex":"https://openalex.org/W2118498286","doi":"https://doi.org/10.1109/tcad.2010.2089569","mag":"2118498286"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2089569","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2089569","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049048133","display_name":"Yifang Liu","orcid":"https://orcid.org/0000-0003-3800-5512"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]},{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yifang Liu","raw_affiliation_strings":["Google, Inc., Mountain View, CA, USA","Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Google, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I1291425158"]},{"raw_affiliation_string":"Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029632511","display_name":"Rupesh S. Shelar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rupesh S. Shelar","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5049048133"],"corresponding_institution_ids":["https://openalex.org/I1291425158","https://openalex.org/I91045830"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.14770758,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"30","issue":"3","first_page":"416","last_page":"426"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.8219617605209351},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.7022933959960938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6838213205337524},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.6166466474533081},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5479961037635803},{"id":"https://openalex.org/keywords/relaxation","display_name":"Relaxation (psychology)","score":0.5479793548583984},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5223991870880127},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45384496450424194},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.37886273860931396},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3628530204296112},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3194275498390198},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.24819308519363403},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22269877791404724}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.8219617605209351},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.7022933959960938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6838213205337524},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.6166466474533081},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5479961037635803},{"id":"https://openalex.org/C2776029896","wikidata":"https://www.wikidata.org/wiki/Q3935810","display_name":"Relaxation (psychology)","level":2,"score":0.5479793548583984},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5223991870880127},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45384496450424194},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.37886273860931396},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3628530204296112},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3194275498390198},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.24819308519363403},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22269877791404724},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C77805123","wikidata":"https://www.wikidata.org/wiki/Q161272","display_name":"Social psychology","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2010.2089569","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2089569","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.674.8044","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.674.8044","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://static.googleusercontent.com/media/research.google.com/en/us/pubs/archive/42859.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1980008391","https://openalex.org/W1996746141","https://openalex.org/W2002403654","https://openalex.org/W2006152335","https://openalex.org/W2094806828","https://openalex.org/W2100735755","https://openalex.org/W2118182815","https://openalex.org/W2123980833","https://openalex.org/W2137406539","https://openalex.org/W2141907973","https://openalex.org/W2142078726","https://openalex.org/W2145126108","https://openalex.org/W2164007237","https://openalex.org/W2166011990","https://openalex.org/W2172629440","https://openalex.org/W2427843410","https://openalex.org/W2787523326","https://openalex.org/W4231119589","https://openalex.org/W4231401555","https://openalex.org/W4244029612","https://openalex.org/W4248136059","https://openalex.org/W6668058724","https://openalex.org/W6677731803","https://openalex.org/W6678381705","https://openalex.org/W6680613659","https://openalex.org/W6717835706"],"related_works":["https://openalex.org/W2156550631","https://openalex.org/W2113835289","https://openalex.org/W3215142653","https://openalex.org/W1487051936","https://openalex.org/W4213145382","https://openalex.org/W315157324","https://openalex.org/W4313341368","https://openalex.org/W4280555049","https://openalex.org/W2763688168","https://openalex.org/W3193692689"],"abstract_inverted_index":{"Technology":[0],"mapping":[1,39,69,136],"and":[2,40,62,70,137],"placement":[3,41,58,71],"have":[4],"a":[5,60,96,112,129],"significant":[6],"impact":[7],"on":[8,108],"delays":[9,101],"in":[10,76,102,111],"standard":[11],"cell-based":[12],"very":[13],"large":[14],"scale":[15],"integrated":[16],"circuits.":[17],"Traditionally,":[18],"these":[19],"steps":[20],"are":[21,44],"applied":[22],"separately":[23],"to":[24,66,98,128],"optimize":[25,99],"the":[26,34,38,64,73,77,81,90,100],"delays,":[27],"possibly":[28],"since":[29],"efficient":[30],"algorithms":[31,119],"that":[32,117],"allow":[33],"simultaneous":[35,67],"exploration":[36],"of":[37,59,93,132],"solution":[42],"spaces":[43],"unknown.":[45],"In":[46],"this":[47],"paper,":[48],"we":[49],"present":[50],"an":[51],"exact":[52],"polynomial":[53],"time":[54],"algorithm":[55,82],"for":[56,72],"delay-optimal":[57],"tree":[61],"extend":[63,80],"same":[65],"technology":[68,115],"optimal":[74],"delay":[75],"tree.":[78],"We":[79],"by":[83],"employing":[84],"Lagrangian":[85],"relaxation":[86],"technique,":[87],"which":[88],"assesses":[89],"timing":[91,121],"criticality":[92],"paths":[94],"beyond":[95],"tree,":[97],"directed":[103],"acyclic":[104],"graphs.":[105],"Experimental":[106],"results":[107],"benchmark":[109],"circuits":[110],"70":[113],"nm":[114],"show":[116],"our":[118],"improve":[120],"significantly":[122],"with":[123],"remarkably":[124],"less":[125],"runtimes":[126],"compared":[127],"competitive":[130],"approach":[131],"iterative":[133],"conventional":[134],"timing-driven":[135],"multilevel":[138],"placement.":[139]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}