{"id":"https://openalex.org/W2111982340","doi":"https://doi.org/10.1109/tcad.2010.2088930","title":"Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis","display_name":"Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis","publication_year":2011,"publication_date":"2011-02-18","ids":{"openalex":"https://openalex.org/W2111982340","doi":"https://doi.org/10.1109/tcad.2010.2088930","mag":"2111982340"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2088930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2088930","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001422055","display_name":"Young-Pyo Joo","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Young-Pyo Joo","raw_affiliation_strings":["Samsung Electronics Limited, Gyeonggi, South Korea","Samsung Electron., Suwon, South Korea#TAB#"],"affiliations":[{"raw_affiliation_string":"Samsung Electronics Limited, Gyeonggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Samsung Electron., Suwon, South Korea#TAB#","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101906662","display_name":"Sungchan Kim","orcid":"https://orcid.org/0000-0002-5887-5606"},"institutions":[{"id":"https://openalex.org/I80611190","display_name":"Jeonbuk National University","ror":"https://ror.org/05q92br09","country_code":"KR","type":"education","lineage":["https://openalex.org/I80611190"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungchan Kim","raw_affiliation_strings":["Chonbuk National University of Korea, Jeonbuk, South Korea","Chonbuk National University, Jeonju, South Korea#TAB#"],"affiliations":[{"raw_affiliation_string":"Chonbuk National University of Korea, Jeonbuk, South Korea","institution_ids":["https://openalex.org/I80611190"]},{"raw_affiliation_string":"Chonbuk National University, Jeonju, South Korea#TAB#","institution_ids":["https://openalex.org/I80611190"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029793438","display_name":"Soonhoi Ha","orcid":"https://orcid.org/0000-0001-7472-9142"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Soonhoi Ha","raw_affiliation_strings":["Seoul National University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Seoul National University, Seoul, South Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5001422055"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":1.0963,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.80080672,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"30","issue":"3","first_page":"468","last_page":"472"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8930398225784302},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8338426351547241},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7250942587852478},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6533870100975037},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6450476050376892},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5589573979377747},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5298514366149902},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5106299519538879},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5013208389282227},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44655245542526245},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.44065165519714355},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.43084433674812317},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4227057099342346}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8930398225784302},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8338426351547241},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7250942587852478},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6533870100975037},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6450476050376892},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5589573979377747},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5298514366149902},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5106299519538879},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5013208389282227},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44655245542526245},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.44065165519714355},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.43084433674812317},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4227057099342346},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcad.2010.2088930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2088930","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.342.9899","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.342.9899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.41999998688697815,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1582823543","https://openalex.org/W2107772170","https://openalex.org/W2114132403","https://openalex.org/W2114925626","https://openalex.org/W2122274805","https://openalex.org/W2154899203","https://openalex.org/W2155131052","https://openalex.org/W2157577358","https://openalex.org/W2158791769","https://openalex.org/W2164181805","https://openalex.org/W2168834504","https://openalex.org/W2170954333","https://openalex.org/W3144369919","https://openalex.org/W4239931236"],"related_works":["https://openalex.org/W2092181573","https://openalex.org/W2576551918","https://openalex.org/W2056447856","https://openalex.org/W2144357574","https://openalex.org/W4230458348","https://openalex.org/W3117657225","https://openalex.org/W1966325333","https://openalex.org/W3198758847","https://openalex.org/W2124403023","https://openalex.org/W1970446888"],"abstract_inverted_index":{"Multiprocessor":[0],"systems-on-chip":[1],"(MPSoCs)":[2],"are":[3],"evolving":[4],"toward":[5],"processor":[6,37],"pool-based":[7,38],"architecture":[8,74,127],"that":[9],"employs":[10],"a":[11,24,56,134],"hierarchical":[12],"on-chip":[13,33,52,71],"network":[14,34],"for":[15,36,102,125],"inter-processor":[16],"and":[17,97,109],"intra-processor":[18],"pool":[19],"communication.":[20],"This":[21],"letter":[22],"presents":[23],"systematic":[25],"exploration":[26,128],"method":[27],"of":[28,51,69,121],"the":[29,67,80,113,126],"cascaded":[30],"bus":[31],"matrix-based":[32],"design":[35,81],"MPSoCs.":[39],"It":[40],"uses":[41],"an":[42,119],"evolutionary":[43],"algorithm":[44],"to":[45,65,78,107],"find":[46],"optimal":[47],"architectures":[48],"in":[49],"terms":[50],"area":[53],"while":[54],"satisfying":[55],"given":[57],"performance":[58,68,104,130],"constraint.":[59],"Since":[60],"simulation":[61],"is":[62],"too":[63],"time-consuming":[64],"evaluate":[66],"complex":[70],"networks":[72],"during":[73],"exploration,":[75],"we":[76,117],"propose":[77],"prune":[79],"space":[82],"efficiently":[83],"using":[84],"two":[85],"novel":[86],"static":[87],"analysis":[88,92,101,115],"techniques:":[89],"1)":[90],"bandwidth":[91],"considering":[93],"task":[94],"execution":[95],"dependences,":[96],"2)":[98],"memory":[99],"contention":[100],"accurate":[103,110],"estimation.":[105],"Thanks":[106],"fast":[108],"evaluation":[111],"by":[112],"proposed":[114],"techniques,":[116],"achieved":[118],"order":[120],"magnitude":[122],"speed":[123],"improvement":[124],"without":[129],"loss,":[131],"compared":[132],"with":[133],"simulation-based":[135],"approach.":[136]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}