{"id":"https://openalex.org/W2163410696","doi":"https://doi.org/10.1109/tcad.2010.2056411","title":"Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs","display_name":"Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs","publication_year":2010,"publication_date":"2010-10-20","ids":{"openalex":"https://openalex.org/W2163410696","doi":"https://doi.org/10.1109/tcad.2010.2056411","mag":"2163410696"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2010.2056411","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2056411","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5107308729","display_name":"Gregory Lucas","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gregory Lucas","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067332736","display_name":"Chen Dong","orcid":"https://orcid.org/0000-0001-7546-3403"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chen Dong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056321228","display_name":"Deming Chen","orcid":"https://orcid.org/0000-0002-3016-0270"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deming Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5107308729"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":0.5773,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.73810493,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"29","issue":"11","first_page":"1818","last_page":"1822"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7551730275154114},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6890888810157776},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6078557372093201},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5664668679237366},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4787256419658661},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.45416009426116943},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4497218430042267},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.4305499494075775},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.27938592433929443},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1891898214817047}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7551730275154114},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6890888810157776},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6078557372093201},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5664668679237366},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4787256419658661},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.45416009426116943},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4497218430042267},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.4305499494075775},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27938592433929443},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1891898214817047},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2010.2056411","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2010.2056411","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W1523051745","https://openalex.org/W1525409241","https://openalex.org/W1964360685","https://openalex.org/W1967709031","https://openalex.org/W1977505713","https://openalex.org/W2005477361","https://openalex.org/W2098290609","https://openalex.org/W2113247137","https://openalex.org/W2126564504","https://openalex.org/W2142910310","https://openalex.org/W3015681923","https://openalex.org/W4229572008","https://openalex.org/W4237955880","https://openalex.org/W6651960422","https://openalex.org/W6676718957"],"related_works":["https://openalex.org/W2137012493","https://openalex.org/W2014521732","https://openalex.org/W3012528295","https://openalex.org/W2024574431","https://openalex.org/W2387100797","https://openalex.org/W2787072969","https://openalex.org/W1522517392","https://openalex.org/W2424214691","https://openalex.org/W3207508415","https://openalex.org/W2150095819"],"abstract_inverted_index":{"Deep":[0],"submicron":[1],"processes":[2],"have":[3],"allowed":[4],"field-programmable":[5],"gate":[6],"arrays":[7],"(FPGAs)":[8],"to":[9,22,26,34,43,55,61,88,91,101,122,141,153],"grow":[10],"in":[11],"complexity":[12],"and":[13,127],"speed.":[14],"However,":[15],"such":[16],"technology":[17],"scaling":[18],"has":[19],"caused":[20],"FPGAs":[21,54],"become":[23],"more":[24],"susceptible":[25],"the":[27,64,125,130,143],"effects":[28],"of":[29,78],"process":[30,45],"variation.":[31],"In":[32,81],"order":[33],"obtain":[35],"sufficient":[36],"yield":[37,146],"values,":[38],"it":[39],"is":[40,51,120,139],"now":[41],"necessary":[42],"consider":[44,92],"variation":[46],"during":[47],"physical":[48],"design.":[49],"It":[50],"common":[52],"for":[53,109,124,129],"contain":[56],"designs":[57,110],"with":[58,105,111],"multi-cycle":[59,93,112,118],"paths":[60],"help":[62],"increase":[63],"performance,":[65],"but":[66],"current":[67],"statistical":[68],"static":[69],"timing":[70,79],"analysis":[71],"(SSTA)":[72],"techniques":[73],"cannot":[74],"support":[75],"this":[76,82,98],"type":[77],"constraint.":[80],"paper,":[83],"we":[84],"propose":[85],"an":[86],"extension":[87],"block-based":[89],"SSTA":[90,100,119],"paths.":[94,113],"We":[95],"then":[96],"use":[97],"new":[99],"optimize":[102],"FPGA":[103],"placement":[104],"our":[106,117],"tool":[107],"VMC-Place":[108,138],"Experimental":[114],"results":[115,134],"show":[116,136],"accurate":[121],"0.59%":[123],"mean":[126],"0.0024%":[128],"standard":[131],"deviation.":[132],"Our":[133],"also":[135],"that":[137],"able":[140],"reduce":[142],"95%":[144],"performance":[145],"clock":[147],"period":[148],"by":[149],"15.36%":[150],"as":[151],"compared":[152],"VPR.":[154]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}